Abstract: A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

Abstract: An oscillator with noise rejection which may be used in a gate array in a semiconductor chip including a first amplifier circuit, a circuit, for connecting an external feedback element (crystal) across the input and inverting output of the first amplifier circuit for generating and amplifying a sine wave, and a circuit connected to the inverting output of the first amplifier circuit for generating a square wave with the duty cycle thereof being proportional to the difference between the center of the voltage swing of the amplified sine wave and a reference voltage. In a preferred embodiment, the first amplifier circuit and the generating circuit each include a current switch. A voltage reference network is provided to set the reference voltage for the current switch in the generating circuit to the center of the voltage swing of the sine wave applied to that current switch. This results in a 50% duty cycle square wave for the output signal.

Abstract: The disclosure is directed to integrated circuit chips and particularly to "gate array", or "master slices" whereon one or more circuits drive a highly capacitive on chip wiring net. The driving circuits are modified and a compensation circuit coupled to the highly capacitive on chip wiring net to mitigate the burden caused by the high capacitance. The integrated circuit structure also contains efficiently positioned on each chip a number of compensation circuits which are readily connectable during the fabrication of the chip. The employment of one, or a number of, on chip compensation circuits does not materially increase the chip power consumption.

Abstract: A circuit for enhancing the ability of digital circuits to drive highly capacitive loads is disclosed. The circuit has particular utility when employed with logic circuits such as "TTL" (Transistor-Transistor Logic) and "DTL" (Diode-Transistor Logic).