Abstract: In a data processing system, a stack mechanism creates a stack of operands in a series of memory locations. The memory locations are grouped into stack frames corresponding to the operands included within individual procedures executed by a processing unit of the data processing system. The stack has a maximum number of allocatable storage locations with the actual physical size of the stack being equal to the total number of operands stored therein. The size of the stack is dynamically alterable to conserve usable storage locations in the memory and accessing of operands within a stack frame can be relative to the top or bottom of the stack frame.

Abstract: A data processing system includes a microprogram controlled central processing unit that executes instructions. The instruction words include a data type field for identifying the type of operand processed during the execution of the instruction. The data type field signals and a number of control signals are applied to the address terminals of a read only memory. The read only memory output signals are tested by microwords of a microprogram to branch to firmware routines to process the operand type.

Abstract: A decoding logic system in a logic control system of a data processing system is disclosed, wherein the data processing system is comprized of a main memory unit communicating with the logic control system by way of a common communication bus, and wherein the logic control system and a CPU (central processing unit) communicate by way of a local communication bus. In response to a CPU request, CPU instructions stored in the main memory unit are received by the logic decoding system, and presented to the CPU in such a manner as to accommodate both memory bit and CPU computed bit modifications to the instructions during instruction execution, while avoiding interruptions in CPU activity caused by information transfer delays internal to the logic decoding system. Instruction modification also may be effected by incrementing or decrementing the instructions under firmware control.

Abstract: A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.

Abstract: A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.

Abstract: A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.

Abstract: This disclosure relates to a control system for transferring binary words from a memory system. One thirty two bit double word may be loaded into a selected two of four sixteen bit registers. As a first of the two selected registers is read, another thirty two bit word may be loaded into the unselected registers. Alternatively, sixteen bit single words may be loaded into and read from the registers. When a word has procedural information, it is read from the registers onto a CPU control bus via a multiplexer. When a word is an encoded computer instruction to the CPU, it is read from the registers into a logic unit via a multiplexer. A decoded instruction from the logic unit is read onto a CPU control bus.

Abstract: A data processing system includes a memory subsystem for storing operands and instructions and a central processing unit (CPU) for manipulating the operands by executing the instructions. The CPU includes a control store for generating signals for controlling the CPU operation. Shifters made up of multiplexers shift operands between an outer bus and a write bus in response to control store signals. The multiplexers shift the operands left or right 1, 2 or 4-bit positions including open shifts and circular shifts and also perform byte position shifting and twinning.

Abstract: A cache memory including an even data store for storing data words associated with even address numbers and an odd data store for storing data words associated with odd address numbers, a local bus for transferring a low order data word and a high order data word simultaneously from the cache memory to a system element requesting the transfer of a pair of data words through the supplying of a single address number request, and a data steering multiplexer for supplying the data word associated with the memory request number, as outputted from either the odd or even cache data store to the low order data word transfer portion of the local bus and the other of the pair of data words outputted from the odd or even data store to the high order data word transfer portion of the local bus.

Abstract: A technique and apparatus for storing data and addressing stored data in a memory from which multiple words of data are to be retrieved in parallel is disclosed. The memory is addressed by providing the address of the first of N consecutive words to be retrieved in parallel. The data is stored in memory in physical data words which contain N logical data words such that the addressing of one physical data word will result in N logical data words being read in parallel from the memory. Each physical data word contains the contents of the logical data word having the same address as that of the physical data word in its leftmost position followed in the next right position by the contents of the logical data word having the next higher address, and so on until the rightmost position of the physical data word contains the contents of the logical data word with an address equal to the physical data word address plus N-1.

Abstract: A cache memory for use in a data processing system wherein data words identified by even address numbers are stored separately from data words associated with odd address numbers to enable the simultaneous transfer of two successively addressed data words to or from the cache memory by the transferring of a data word associated with an odd address number and a data word associated with an even address number.

Abstract: A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a first delay line coupled to an inverter by using a multitapped second delay line to delay the rectangular wave train by selectable predetermined period. A control signal is formed which when fed into the generator produces a second rectangular wave train with a clock cycle period equal to the rectangular wave train clock cycle period plus the period of the second selected predetermined delay. By serially connecting a multitapped third delay line in series with the second delay line and by providing a first switch to select one of the outputs from said third delay line, the clock cycle period of the clock system may be adjusted.

Abstract: In a data processing system, a system memory includes first memory modules having a data path of a first bit width and second memory modules having a data path of a second bit width with the first bit width being less than the second bit width. A central subsystem includes a cache memory unit and processing units for initiating requests for data transfers of the second bit width between the system memory and the subsystem processing units. An interface coupling the system memory and the central subsystem for bidirectional data transfers generates, in response to a memory request of a second bit width wherein the requested data is stored in a first memory module, additional memory requests until sufficient data has been retrieved from the system memory to satisfy the central subsystem request.

Abstract: A control store included in a data processing system for storing microinstructions in a plurality of microinstructions storage locations is organized in two parts, an upper bank and a lower bank. The lower bank is directly addressed by a portion of the currently addressed control store word, whereas the upper bank is addressed by use of a multiplexer, with inputs thereto coupled from various logic elements. Apparatus is included to determine which part of the control store will be selected and to allow such determination at a time substantially after the addresses for the first and second parts have been received by the control store.

Abstract: In a data processing system, a central processor unit requests procedural data words or non-procedural data words stored in the system memory. A control store device executes firmware instructions including a local bus field for controlling the transfer of the requested procedural data words and non-procedural data words to the central processor unit.

Abstract: A data processing system includes a first memory for storing microinstructions in a first plurality of storage locations and second memory for storing microinstructions in a second plurality of storage locations. A central processor executing a series of addressed microinstructions to control the functions performed by this system generates the address of the next microinstruction to be executed in series as well as a next address selection signal. Addressing circuitry concurrently applies the next address generated by the processor to address inputs of each of the first memory and the second memory. After a predetermined delay, either the first memory or the second memory is selected to output an address microinstruction responsive to the value of the next address selection signal.

Abstract: A first bank or a second bank of storage locations of a control store of a data processing system is enabled in response to one of a plurality of test signals received as parallel inputs by two multiplexer devices. Only one of the multiplexers is enabled at a given time in response to the polarity of one of the test signals selected from the inputs of the multiplexer devices.

Abstract: One or more queue structures in a data processing system may include a threaded list of frames which are enqueued or dequeued from the list in accordance with four instructions wherein each list is tied to a so-called lock or control frame with synchronization for multiple processing units. Multiple lock frames and accordingly multiple lists of frames may be coupled in the system for the purpose of accomplishing the various tasks necessary.

Abstract: A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a delay line coupled to an INVERTER. By using a second delay line to delay the rectangular wave by a selectable predetermined delay period, a control signal is formed which when fed into the generator produces a second rectangular wave train with a clock cycle period equal to that of the rectangular wave clock cycle period plus the period of the second predetermined delay. The addition of a synchronization circuit permits the clock cycle period to be dynamically selected during a clock cycle. This provides a rectangular train with the period of each clock cycle being any of the predetermined clock cycle periods independent of the clock cycle period of preceding or succeeding clock cycles.

Abstract: A final effective address of an operand is generated in a microprogrammed data processing system by use of a base address register which may include an unindexed address, an index register which may include an indexed address value, an instruction register which may include an instruction word, which instruction word provides control over the addressing of a control store dependent upon the state of a selected one of a plurality of test conditions. One of the test conditions indicating whether some of the addressing values used in the generation of the effective address are in a short address format or in a long address format. The address control store word provides signals for controlling the operation of the system, including the branch in between such major operations as instruction fetching, addressing, reading, writing, and execution as well as branching between minor operations which are included in the major operations.