Patents by Inventor Philip F. S. Swab
Philip F. S. Swab has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11502249Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.Type: GrantFiled: September 22, 2020Date of Patent: November 15, 2022Assignee: Hefei Reliance Memory LimitedInventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
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Patent number: 10833125Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.Type: GrantFiled: May 14, 2019Date of Patent: November 10, 2020Assignee: Hefei Reliance Memory LimitedInventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
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Patent number: 10797106Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.Type: GrantFiled: May 14, 2019Date of Patent: October 6, 2020Assignee: Hefei Reliance Memory LimitedInventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
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Patent number: 10340312Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.Type: GrantFiled: October 30, 2017Date of Patent: July 2, 2019Assignee: Hefei Reliance Memory LimitedInventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
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Patent number: 9806130Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.Type: GrantFiled: December 29, 2016Date of Patent: October 31, 2017Assignee: Unity Semiconductor CorporationInventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
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Patent number: 9570515Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.Type: GrantFiled: September 10, 2015Date of Patent: February 14, 2017Assignee: UNITY SEMICONDUCTOR CORPORATIONInventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
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Patent number: 9570165Abstract: A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element, and a two-terminal switching element. The first resistive memory element is electrically coupled to the second resistive memory element and to the switching element at a common node.Type: GrantFiled: December 11, 2014Date of Patent: February 14, 2017Assignee: Rambus Inc.Inventors: Deepak Chandra Sekar, Gary Bela Bronner, Christophe J. Chevallier, Lidia Vereen, Philip F. S. Swab, Elizabeth Friend, Mehmet Gunhan Ertosun
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Patent number: 9159408Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.Type: GrantFiled: January 29, 2014Date of Patent: October 13, 2015Assignee: UNITY SEMICONDUCTOR CORPORATIONInventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
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Publication number: 20120064691Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.Type: ApplicationFiled: November 21, 2011Publication date: March 15, 2012Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: DARRELL RINERSON, WAYNE KINNEY, EDMOND R. WARD, STEVE KUO-REN HSIA, STEVEN W. LONGCOR, CHRISTOPHE J. CHEVALLIER, JOHN SANCHEZ, PHILIP F. S. SWAB
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Publication number: 20120033481Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.Type: ApplicationFiled: October 13, 2011Publication date: February 9, 2012Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: DARRELL RINERSON, WAYNE KINNEY, EDMOND R. WARD, STEVE KUO-REN HSIA, STEVEN LONGCOR, CHRISTOPHE J. CHEVALLIER, JOHN SANCHEZ, PHILIP F. S. SWAB
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Publication number: 20090045390Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.Type: ApplicationFiled: October 1, 2008Publication date: February 19, 2009Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: Darrel Rinerson, Wayne Kinney, Edmond R. Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe J. Chevallier, John Sanchez, Philip F. S. Swab
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Patent number: 6972985Abstract: A memory including a memory element having islands is provided. The memory has address decoding circuitry and an array of memory plugs. The memory plugs include memory element that have island structures of a first material within the bulk of a second material. The island structures are typically nanoparticles. The memory plugs can be placed in a first resistive state at a first write voltage, placed in a second resistive state at a second write voltage, and have its resistive state determined at a read voltage.Type: GrantFiled: June 15, 2004Date of Patent: December 6, 2005Inventors: Darrell Rinerson, Christophe J. Chevallier, Philip F. S. Swab, Steve Kuo-Ren Hsia, John E. Sanchez, Jr., Steven W. Longcor