Patents by Inventor Philip F. S. Swab

Philip F. S. Swab has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090045390
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Application
    Filed: October 1, 2008
    Publication date: February 19, 2009
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Darrel Rinerson, Wayne Kinney, Edmond R. Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe J. Chevallier, John Sanchez, Philip F. S. Swab
  • Publication number: 20080293196
    Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
    Type: Application
    Filed: June 30, 2008
    Publication date: November 27, 2008
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Darrell Rinerson, Wayne Kinney, Edmond R. Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe J. Chevallier, John Sanchez, Philip F.S. Swab
  • Patent number: 6972985
    Abstract: A memory including a memory element having islands is provided. The memory has address decoding circuitry and an array of memory plugs. The memory plugs include memory element that have island structures of a first material within the bulk of a second material. The island structures are typically nanoparticles. The memory plugs can be placed in a first resistive state at a first write voltage, placed in a second resistive state at a second write voltage, and have its resistive state determined at a read voltage.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: December 6, 2005
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Philip F. S. Swab, Steve Kuo-Ren Hsia, John E. Sanchez, Jr., Steven W. Longcor