Patents by Inventor Philip G. Williams
Philip G. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9792208Abstract: A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel.Type: GrantFiled: January 31, 2014Date of Patent: October 17, 2017Assignee: International Business Machines CorporationInventors: Sanjeev Ghai, Guy Lynn Guthrie, Hien Minh Le, Hugh Shen, Philip G. Williams
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Patent number: 9471491Abstract: A technique for operating a high-availability (HA) data processing system includes, in response to receiving an HA logout indication at a cache, initiating a walk of the cache to locate cache lines in the cache that include HA data. In response to determining that a cache line includes HA data, an address of the cache line is logged in a first portion of a buffer in the cache. In response to the first portion of the buffer reaching a determined fill level, contents of the first portion of the buffer are logged to another memory. In response to all cache lines in the cache being walked, the cache walk is terminated.Type: GrantFiled: November 6, 2013Date of Patent: October 18, 2016Assignee: International Business Machines CorporationInventors: Sanjeev Ghai, Guy Lynn Guthrie, Hien Minh Le, Hugh Shen, Philip G. Williams
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Patent number: 9430382Abstract: A technique for operating a high-availability (HA) data processing system includes, in response to receiving an HA logout indication at a cache, initiating a walk of the cache to locate cache lines in the cache that include HA data. In response to determining that a cache line includes HA data, an address of the cache line is logged in a first portion of a buffer in the cache. In response to the first portion of the buffer reaching a determined fill level, contents of the first portion of the buffer are logged to another memory. In response to all cache lines in the cache being walked, the cache walk is terminated.Type: GrantFiled: January 31, 2014Date of Patent: August 30, 2016Assignee: International Business Machines CorporationInventors: Sanjeev Ghai, Guy Lynn Guthrie, Hien Minh Le, Hugh Shen, Philip G. Williams
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Patent number: 9336142Abstract: A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel.Type: GrantFiled: November 6, 2013Date of Patent: May 10, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sanjeev Ghai, Guy Lynn Guthrie, Hien Minh Le, Hugh Shen, Philip G. Williams
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Publication number: 20150127906Abstract: A technique for operating a high-availability (HA) data processing system includes, in response to receiving an HA logout indication at a cache, initiating a walk of the cache to locate cache lines in the cache that include HA data. In response to determining that a cache line includes HA data, an address of the cache line is logged in a first portion of a buffer in the cache. In response to the first portion of the buffer reaching a determined fill level, contents of the first portion of the buffer are logged to another memory. In response to all cache lines in the cache being walked, the cache walk is terminated.Type: ApplicationFiled: November 6, 2013Publication date: May 7, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sanjeev Ghai, Guy Lynn Guthrie, Hien Minh Le, Hugh Shen, Philip G. Williams
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Publication number: 20150127910Abstract: A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel.Type: ApplicationFiled: January 31, 2014Publication date: May 7, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sanjeev Ghai, Guy Lynn Guthrie, Hien Minh Le, Hugh Shen, Philip G. Williams
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Publication number: 20150127908Abstract: A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel.Type: ApplicationFiled: November 6, 2013Publication date: May 7, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sanjeev Ghai, Guy Lynn Guthrie, Hien Minh Le, Hugh Shen, Philip G. Williams
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Publication number: 20150127909Abstract: A technique for operating a high-availability (HA) data processing system includes, in response to receiving an HA logout indication at a cache, initiating a walk of the cache to locate cache lines in the cache that include HA data. In response to determining that a cache line includes HA data, an address of the cache line is logged in a first portion of a buffer in the cache. In response to the first portion of the buffer reaching a determined fill level, contents of the first portion of the buffer are logged to another memory. In response to all cache lines in the cache being walked, the cache walk is terminated.Type: ApplicationFiled: January 31, 2014Publication date: May 7, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sanjeev Ghai, Guy Lynn Guthrie, Hien Minh Le, Hugh Shen, Philip G. Williams
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Patent number: 8327073Abstract: A second lower level cache receives an LCO command issued by a first lower level cache on an interconnect fabric. The LCO command indicates an address of a victim cache line to be castout from the first lower level cache and indicates that the second lower level cache is an intended destination of the victim cache line. The second lower level cache determines whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command. In response to determining not to accept the victim cache line, the second lower level cache provides a coherence response to the LCO command refusing the identified victim cache line. In response to determining to accept the victim cache line, the second lower level cache updates an entry corresponding to the identified victim cache line.Type: GrantFiled: April 9, 2009Date of Patent: December 4, 2012Assignee: International Business Machines CorporationInventors: Guy L. Guthrie, Harmony L. Helterhoff, Thomas L. Jeremiah, Alvan W. Ng, William J. Starke, Jeffrey A. Stuecheli, Philip G. Williams
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Publication number: 20100262784Abstract: A second lower level cache receives an LCO command issued by a first lower level cache on an interconnect fabric. The LCO command indicates an address of a victim cache line to be castout from the first lower level cache and indicates that the second lower level cache is an intended destination of the victim cache line. The second lower level cache determines whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command. In response to determining not to accept the victim cache line, the second lower level cache provides a coherence response to the LCO command refusing the identified victim cache line. In response to determining to accept the victim cache line, the second lower level cache updates an entry corresponding to the identified victim cache line.Type: ApplicationFiled: April 9, 2009Publication date: October 14, 2010Applicant: International Business Machines CorporationInventors: Guy L. Guthrie, Harmony L. Helterhoff, Thomas L. Jeremiah, Alvan W. Ng, William J. Starke, Jeffrey A. Stuecheli, Philip G. Williams
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Publication number: 20100100683Abstract: A processing unit for a multiprocessor data processing system includes a processor core and a cache hierarchy coupled to the processor core to provide low latency data access. The cache hierarchy includes an upper level cache coupled to the processor core and a lower level victim cache coupled to the upper level cache. In response to a prefetch request of the processor core that misses in the upper level cache, the lower level victim cache determines whether the prefetch request misses in the directory of the lower level victim cache and, if so, allocates a state machine in the lower level victim cache that services the prefetch request by issuing the prefetch request to at least one other processing unit of the multiprocessor data processing system.Type: ApplicationFiled: October 22, 2008Publication date: April 22, 2010Applicant: International Business Machines CorporationInventors: Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli, Philip G. Williams
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Patent number: 7500065Abstract: A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.Type: GrantFiled: December 13, 2007Date of Patent: March 3, 2009Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, William John Starke, Derek Edward Williams, Philip G. Williams
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Patent number: 7490202Abstract: A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.Type: GrantFiled: December 13, 2007Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, William John Starke, Derek Edward Williams, Philip G. Williams
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Patent number: 7337280Abstract: A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.Type: GrantFiled: February 10, 2005Date of Patent: February 26, 2008Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, William John Starke, Derek Edward Williams, Philip G. Williams
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Patent number: 6160128Abstract: Novel acetylating and tritioacetylating reagents suitable for preparation of nonlabelled and radiolabelled organic compounds. N-acetoxynaphthalimide, N-tritioacetoxyphthalimide, N-tritioacetoxysuccinimide, N-tritioacetoxynaphthalimide and processes of their preparation. The invention also concerns synthesis of nonlabelled acetylated and tritioacetylated organic compounds from precursors containing a free --NH.sub.2, --SH or --OH group.Type: GrantFiled: October 23, 1998Date of Patent: December 12, 2000Assignee: The Regents of the University of CaliforniaInventors: Manoucher Saljoughian, Hiromi Morimoto, Philip G. Williams, Chit Than
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Patent number: 5186868Abstract: Reagents and processes for reductively introducing deuterium or tritium into organic molecules are described. The reagents are deuterium or tritium analogs of trialkyl boranes, borane or alkali metal aluminum hydrides. The process involves forming these reagents in situ from alkali metal tritides or deuterides.Type: GrantFiled: April 5, 1990Date of Patent: February 16, 1993Assignee: The Regents of the University of CaliforniaInventors: Hendrik Andres, Hiromi Morimoto, Philip G. Williams