Patents by Inventor Philip Garrou

Philip Garrou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150327388
    Abstract: An active component array includes a target substrate having one or more contacts formed on a side of the target substrate, and one or more printable active components distributed over the target substrate. Each active component includes an active layer having a top side and an opposing bottom side and one or more active element(s) formed on or in the top side of the active layer. The active element(s) are electrically connected to the contact(s), and the bottom side is adhered to the target substrate. Related fabrication methods are also discussed.
    Type: Application
    Filed: May 18, 2015
    Publication date: November 12, 2015
    Inventors: Etienne Menard, Christopher Bower, Matthew Meitl, Philip Garrou
  • Patent number: 9049797
    Abstract: An active component array includes a target substrate having one or more contacts formed on a side of the target substrate, and one or more printable active components distributed over the target substrate. Each active component includes an active layer having a top side and an opposing bottom side and one or more active element(s) formed on or in the top side of the active layer. The active element(s) are electrically connected to the contact(s), and the bottom side is adhered to the target substrate. Related fabrication methods are also discussed.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: June 2, 2015
    Assignee: Semprius, Inc.
    Inventors: Etienne Menard, Christopher Bower, Matthew Meitl, Philip Garrou
  • Patent number: 8486765
    Abstract: A method for making a structure for thermal management of circuit devices. The method provides a first substrate and a second substrate where at least one of the first and second substrates includes a circuit element. The method forms in at least one of the first substrate and the second substrate an entrance through-hole extending through a thickness of the first substrate or the second substrate, forms in at least one of the first substrate and the second substrate an exit through-hole extending through a thickness of the first substrate or the second substrate, forms respective bonding elements on at least one of the first and second substrates, and bonds the first and second substrates at the respective bonding elements to form a seal between the first and second substrates and to form a first coolant channel in between the first and second substrates.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: July 16, 2013
    Assignee: Research Triangle Institute
    Inventors: Philip Garrou, Charles Kenneth Williams, Christopher A. Bower
  • Publication number: 20130153277
    Abstract: An active component array includes a target substrate having one or more contacts formed on a side of the target substrate, and one or more printable active components distributed over the target substrate. Each active component includes an active layer having a top side and an opposing bottom side and one or more active element(s) formed on or in the top side of the active layer. The active element(s) are electrically connected to the contact(s), and the bottom side is adhered to the target substrate. Related fabrication methods are also discussed.
    Type: Application
    Filed: March 22, 2011
    Publication date: June 20, 2013
    Inventors: Etienne Menard, Christopher Bower, Matthew Meitl, Philip Garrou
  • Publication number: 20120048596
    Abstract: A method for making a structure for thermal management of circuit devices. The method provides a first substrate and a second substrate where at least one of the first and second substrates includes a circuit element. The method forms in at least one of the first substrate and the second substrate an entrance through-hole extending through a thickness of the first substrate or the second substrate, forms in at least one of the first substrate and the second substrate an exit through-hole extending through a thickness of the first substrate or the second substrate, forms respective bonding elements on at least one of the first and second substrates, and bonds the first and second substrates at the respective bonding elements to form a seal between the first and second substrates and to form a first coolant channel in between the first and second substrates.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 1, 2012
    Applicant: Research Triangle Institute
    Inventors: Philip GARROU, Charles Kenneth Williams, Christopher A. Bower
  • Patent number: 8035223
    Abstract: A structure and method for thermal management of integrated circuits. The structure for thermal management of integrated circuits includes first and second substrates bonded together, at least one of the first and second substrates including at least one circuit element, an entrance through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, an exit through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, a bonding element forming a seal between the first and second substrates and forming a space between the first and second substrate, and a coolant channel formed in the space between the first and second substrates such that a fluid entering the entrance through-hole transits the coolant channel and the exit through-hole to provide cooling to the circuit element.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: October 11, 2011
    Assignee: Research Triangle Institute
    Inventors: Philip Garrou, Charles Kenneth Williams, Christopher A. Bower
  • Publication number: 20090057879
    Abstract: A structure and method for thermal management of integrated circuits. The structure for thermal management of integrated circuits includes first and second substrates bonded together, at least one of the first and second substrates including at least one circuit element, an entrance through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, an exit through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, a bonding element forming a seal between the first and second substrates and forming a space between the first and second substrate, and a coolant channel formed in the space between the first and second substrates such that a fluid entering the entrance through-hole transits the coolant channel and the exit through-hole to provide cooling to the circuit element.
    Type: Application
    Filed: August 28, 2007
    Publication date: March 5, 2009
    Applicant: Reseach Triangle Institute
    Inventors: Philip GARROU, Charles Kenneth WILLIAMS, Christopher A. BOWER
  • Publication number: 20060254502
    Abstract: Improved methods and articles providing conformal coatings for a variety of devices including electronic, semiconductor, and liquid crystal display devices. Peptide formulations which bind to nanoparticles and substrates, including substrates with trenches and vias, to provide conformal coverage as a seed layer. The seed layer can be further enhanced with use of metallic films deposited on the seed layer. Seed layers can be characterized by AFM measurements and improved seed layers provide for better enhancement layers including lower resistivity in the enhancement layer. Peptides can be identified by phage display.
    Type: Application
    Filed: November 16, 2005
    Publication date: November 16, 2006
    Applicant: Cambrios Technologies Corporation
    Inventors: Philip Garrou, Michael Knapp, Hash Pakbaz, Florian Pschenitzka, Xina Quan, Michael Spaid