Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

Abstract: A method of electronic computing, and more specifically, a method of design of cache hierarchies in 3-dimensional chips, and a cache hierarchy resulting therefrom, including a physical arrangement of bits in cache hierarchies implemented in 3 dimensions such that the planar wiring required in the busses connecting the levels of the hierarchy is minimized. In this way, the data paths between the levels are primarily the vias themselves, which leads to very short, hence fast and low power busses.

Abstract: Apparatus for passively tracking expired data in a dynamic memory includes an error encoding circuit operative to receive an input data word and to generate an encoded data word which is stored in the dynamic memory. The apparatus further includes a decoding circuit operative to receive an encoded data word from the dynamic memory, to detect at least one or more unidirectional errors in the input data word read from the dynamic memory, and to generate an error signal when at least one error is detected, the error signal indicating that the input data word contains expired data. Control circuitry included in the apparatus is configured for initiating one or more actions in response to the error signal.

Abstract: A system and method for the superimposition of differential signals on binary signals in a memory system. The technique can be performed on busses, and in many kinds of storage media. It can be accomplished in many ways depending on the noise that is to be tolerated, and depending on the sophistication of the encoding means.

Abstract: Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.

Abstract: A cache memory system for use with an external cache system comprising at least one data array includes one or more cache data arrays and corresponding cache directory arrays. The cache memory system operates in one of at least two modes of operation. In a first mode of operation, the cache data arrays store data relating to directory information stored in the corresponding cache directory arrays. In a second mode of operation, at least a portion of the cache data arrays stores directory information corresponding to the at least one data array of the external cache system.

Abstract: A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for sending and receiving data to each other. An at least one swapper circuit is electrically connected to the bus at a connection point between the plurality of entities. The at least one swapper circuit includes means for timing data transfer between a send data mode and a receive data mode and sending and receiving data during the respective modes. The at least one swapper circuit includes a routing means for receiving data simultaneously from the plurality of entities and then sending data simultaneously to the plurality of entities without colliding data.

Abstract: A system and method for reducing the number of refresh actions needed to maintain data in a DRAM, by restoring only those cells which haven't been read from or written to within an allotted data retention time. One embodiment describes a restore tracking system as applied to a DRAM cache. The restore tracking system can alternatively be applied to any memory architecture having duplication of information. For example, the number of refresh actions needed to maintain data entries in a DRAM can be reduced by recording and updating a refresh status of one or more of the data entries in the DRAM; and invalidating those data entries having an expired status. Thus, more memory bandwidth can be made available to a computer system.

Abstract: A nonvolatile memory system is described. The system includes ferroelectric memory cells each comprising a pair of metal plates and a ferroelectric material therebetween. Data are stored in the cells by applying an electric field corresponding to the desired data value across a given cell, thereby setting the polarity of the ferroelectric material to a given state. A datum is read from a cell by a mechanical force to the ferroelectric material and sensing charge induced on one of the cells.

Abstract: The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips. The memory cells use three-dimensional (3D) SRAM structures. Two kinds of 3D logic cells are disclosed. 3D form of the differential cascode voltage switch (DCVS) architecture, and a 3D form of the DCVS with pass gate (DCVSPG) logic architecture. A high density “system on chip” architecture is described. The high density is achieved by locating large PMOS transistors in the TF Si layer, and the fast NMOS transistors in a bulk Si wafer layer. A single process sequence to simultaneously make the logic and memory circuits on the IC chip is also described.

Abstract: The present invention describes the use of large thin film (TF) capacitors having capacitance C made in a separate set of TF layers ABOVE the Si and wiring levels of an integrated circuit (IC). This C is very large. This invention describes a two-level IC architecture in which a metal/insulator/metal (MIM) capacitor structure comprises the upper level, and CMOS logic and memory circuits made in the Si wafer substrate comprise the lower level. The added thin film capacitance serves to stabilize the power supply voltage at a constant level during GHz IC operation.

Abstract: The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips. The memory cells use three-dimensional (3D) SRAM structures. Two kinds of 3D logic cells are disclosed. 3D form of the differential cascode voltage switch (DCVS) architecture, and a 3D form of the DCVS with pass gate (DCVSPG) logic architecture. A high density “system on chip” architecture is described. The high density is achieved by locating large PMOS transistors in the TF Si layer, and the fast NMOS transistors in a bulk Si wafer layer. A single process sequence to simultaneously make the logic and memory circuits on the IC chip is also described.

Abstract: A portable computing device includes a processing unit coupled with a keyboard, a recording medium, and a display. The keyboard and the recording medium form portions of a support structure of the device and are generally directed in different directions. The recording medium is configured to receive input from a stylus operated by a user. The display is movable (e.g., pivotable and/or translatable) about the support structure to selectively suit use of the display in conjunction with the keyboard or use of the display in conjunction with the stylus and the recording medium. An elongatable arm can serve to connect the display with the support structure.

Abstract: A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for sending and receiving data to each other. An at least one swapper circuit is electrically connected to the bus at a connection point between the plurality of entities. The at least one swapper circuit includes means for timing data transfer between a send data mode and a receive data mode and sending and receiving data during the respective modes. The at least one swapper circuit includes a routing means for receiving data simultaneously from the plurality of entities and then sending data simultaneously to the plurality of entities without colliding data.

Abstract: A memory design which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built into the memory's decoding circuitry. The introduction of an internal address generation facility simplifies extraneous control of typical requesters built into a memory system. The memory design also reduces power consumed by requests which exploit the memory's internal address generation facility. Power consumption is further reduced in a set associative cache memory system by enabling one set of sense amplifiers during an incremental fetch.

Abstract: A nonvolatile memory system is described. The system includes ferroelectric memory cells each comprising a pair of metal plates and a ferroelectric material therebetween. Data are stored in the cells by applying an electric field corresponding to the desired data value across a given cell, thereby setting the polarity of the ferroelectric material to a given state. A datum is read from a cell by a mechanical force to the ferroelectric material and sensing charge induced on one of the cells.

Abstract: A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.

Abstract: A system and method for the superimposition of differential signals on binary signals. The technique can be performed on busses, and in many kinds of storage media. It can be accomplished in many ways depending on the noise that is to be tolerated, and depending on the sophistication of the encoding means.

Abstract: A method for accessing a cache memory which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built into the memory's decoding circuitry. The introduction of an internal address generation facility simplifies extraneous control of typical requesters built into a memory system. The method also reduces power consumed by requests which exploit the memory's internal address generation facility. Power consumption is further reduced in a set associative cache memory system by enabling one set of sense amplifiers during an incremental fetch.

Abstract: A system and method for the superimposition of differential signals on binary signals. The technique can be performed on busses, and in many kinds of storage media. It can be accomplished in many ways depending on the noise that is to be tolerated, and depending on the sophistication of the encoding means.