Abstract: A duo-binary and/or binary data slicer has a data input (10) coupled via a capacitor (C1) to a d.c. restoring circuit (A2 to Q6 and Q9 to Q13) d.c. reference level is superimposed on the data signal. A sample and hold circuit (C2, Q15 to Q22) is arranged to sample the data signal and provide a voltage related to the upper and lower peak value. A divider (R16-R19) is coupled between the d.c. reference level and the voltage related to the upper and lower peak value and provides intermediate output voltages (DU, DL, B) relating to duo-binary and/or binary level for determining the slicing levels.

Abstract: A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one conductivity type adjacent a given surface (3a) of a semiconductor body (3) to provide, for both the enhancement mode (1) and for the depletion mode (2) IGFET, a second region (5) of the opposite conductivity type adjacent the given surface, a source region (9) of a first conductivity type adjacent the given surface (3a) and surrounded by the second region (5) and a drain region (10) of the first conductivity type having a relatively lightly doped drain extension region (11) adjacent the given surface and extending toward the source region (9).

Abstract: A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one conductivity type adjacent a given surface (3a) of a semiconductor body (3) to provide, for both the enhancement mode (1) and for the depletion mode (2) IGFET, a second region (5) of the opposite conductivity type adjacent the given surface, a source region (9) of a first conductivity type adjacent the given surface (3a) and surrounded by the second region (5) and a drain region (10) of the first conductivity type having a relatively lightly doped drain extension region (11) adjacent the given surface and extending toward the source region (9).

Abstract: A television receiver has an a.f.c. arrangement for ensuring the correct tuning of a tuner unit (4) which is tuned to the nominal carrier frequency by a tuning voltage (VT). When the tuner unit (4) is incorrectly tuned to the actual carrier frequency, the a.f.c. system operates in a first mode in which a sweep current produced by a current source (15) is applied by way of a closed switch (16) to an a.f.c. capacitor (17) to produce a swept a.f.c. voltage for the tuner unit (4). The sweep direction is controlled by an RS flip-flop (13) by way of a multiplexer (12) in response to voltage comparators (19, 20) connected to the a.f.c. capacitor (17). When the tuning is sufficiently close such that the received transmission can be correctly decoded, the a.f.c. arrangement goes into a second mode in which the output of a frequency demodulator (6) is applied via the multiplexer (12) to control the current source (15) and hence the voltage across a.f.c. capacitors (17).

Abstract: Low voltage semiconductor devices are integrated monolithically with a high voltage semiconductor device on an electrically conductive substrate. The substrate forms an electrode of the high voltage device and is connected in use to the high voltage terminal of a power supply. The low voltage devices operate from a regulated low voltage supply, which is regulated with reference to the high voltage supply voltage, and not with reference to ground. This reduces the need to isolate the low voltage devices from the conductive substrate. An intelligent power switch circuit constructed in accordance with the invention is suitable for use in automotive and lighting applications.

Abstract: An arrangement for driving a power semiconductor device (1) has an input (12) for receiving a control signal and a control output (11) for connection to the control electrode (9) of the power semiconductor device (1). The semiconductor device connected in series with a load (5) across a power supply (3,6). The arrangement includes an active turn-off device (T67) to achieve fast turn-off of the device (1). The arrangement further includes a threshold detecting means (29) which operates to turn on the semiconductor device in the event of a high voltage transient on the power supply. This reduces the voltage across the semiconductor device and hence reduces power dissipation within the semiconductor during transients. The turn-off device (T67) could be damaged by high transient currents when the threshold detecting means (29) conducts, so a further threshold detecting means (30) acts to disable the turn-off means (T67) during transients.

Abstract: A differential amplifier includes first and second matched field-effect transistors (FETs) (21,22) having their source electrodes connected together and to a current source (2), and their drain electrodes connected respectively to an input and an output of a current mirror circuit (3). The FETs (21,22) are depletion-mode FETs, and the current source comprises parallel-connected third and fourth depletion-mode FETs (25,26) matched to the first and second FETs (21,22). The current source (2) and current mirror (3) act to constrain the first and second FETs (21,22), to operate over a predetermined operating curve, for which they are optimally matched to one another. The differential amplifier may be constructed as an integrated circuit, and may form part of a circuit for sensing current in a power semiconductor device.

Abstract: A speed control system for an a.c. electric motor (1) comprises a microcomputer (6) having an interrupt signal input (INT/TO) to which is coupled the outputs of a detector (10) for detecting zero-crossings of the a.c. supply voltage and a tachogenerator (11) driven by the motor. The microcomputer supplies firing pulses to a triac (2), connected in series with the motor, in response to an overflow of a clocked counter (CT). This counter is suitably preloaded at each zero-crossing. The counter is read each time a tachogenerator pulse occurs and the time which this reading indicates has elapsed since the immediately preceding zero-crossing is stored. A record is also kept in a register (ZCSLTA) of how many zero-crossings occur between each tachogenerator pulse and the next and from this, and the stored times relating to the relevant pulses, the period of the tachogenerator pulses and hence the actual speed of the motor is calculated.