Abstract: Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage, thereby alleviating congestion. Once the buffer chains have been reconstructed, the placement blockage can be removed from the circuit design. In some embodiments, congestion can be alleviated by spreading out buffer chains based on spreading out center of mass lines corresponding to the buffer chains.

Abstract: Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage, thereby alleviating congestion. Once the buffer chains have been reconstructed, the placement blockage can be removed from the circuit design. In some embodiments, congestion can be alleviated by spreading out buffer chains based on spreading out center of mass lines corresponding to the buffer chains.

Abstract: Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage, thereby alleviating congestion. Once the buffer chains have been reconstructed, the placement blockage can be removed from the circuit design. In some embodiments, congestion can be alleviated by spreading out buffer chains based on spreading out center of mass lines corresponding to the buffer chains.

Abstract: Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage, thereby alleviating congestion. Once the buffer chains have been reconstructed, the placement blockage can be removed from the circuit design. In some embodiments, congestion can be alleviated by spreading out buffer chains based on spreading out center of mass lines corresponding to the buffer chains.

Abstract: A system and method for generating physical design of an integrated circuit, based on schematic design. The system includes graphical user interface and integrated circuit design and layout system. The integrated circuit design and layout system creates and analyzes logical slices of the integrated circuit based on the schematic design; creates and edits macros based on the logical slices; and traces and analyzes data paths through the physical design based on the schematic design. The method includes providing the schematic design of the integrated circuit, and generating logical slices of the integrated circuit from the schematic design. The method also includes generating, grouping and manipulating macros, responsive to identification of multiple occurrences of logical slices. The method further includes performing data flow analysis to identify data paths for the physical design, quantifying weight indices for the data paths, and positioning objects in the physical design based on the weight indices.

Abstract: A system and method for generating physical design of an integrated circuit, based on schematic design. The system includes graphical user interface and integrated circuit design and layout system. The integrated circuit design and layout system creates and analyzes logical slices of the integrated circuit based on the schematic design; creates and edits macros based on the logical slices; and traces and analyzes data paths through the physical design based on the schematic design. The method includes providing the schematic design of the integrated circuit, and generating logical slices of the integrated circuit from the schematic design. The method also includes generating, grouping and manipulating macros, responsive to identification of multiple occurrences of logical slices. The method further includes performing data flow analysis to identify data paths for the physical design, quantifying weight indices for the data paths, and positioning objects in the physical design based on the weight indices.