Patents by Inventor Philip Hower

Philip Hower has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090096033
    Abstract: A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor device. At least one upper corner of the insulating trench is a rounded corner in a lateral plane of the substrate.
    Type: Application
    Filed: October 16, 2007
    Publication date: April 16, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharkar, John Lin, Philip Hower, Steven L. Merchant
  • Publication number: 20070045732
    Abstract: The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).
    Type: Application
    Filed: August 3, 2005
    Publication date: March 1, 2007
    Applicant: Texas Instruments Inc.
    Inventors: John Lin, Tony Phan, Philip Hower, William Loftin, Martin Mollat
  • Publication number: 20070029611
    Abstract: The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).
    Type: Application
    Filed: August 2, 2005
    Publication date: February 8, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Tony Phan, William Loftin, John Lin, Philip Hower
  • Publication number: 20070012958
    Abstract: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.
    Type: Application
    Filed: September 22, 2006
    Publication date: January 18, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Philip Hower, David Walch, John Lin, Steven Merchant
  • Publication number: 20060292771
    Abstract: A high voltage field effect transistor device is fabricated. A substrate is provided. Isolation structures and well regions are formed therein. Drain well regions are formed within the well regions. An n-type channel stop resist mask is formed. N-type channel stop regions and n-type surface channel regions are formed. A p-type channel stop resist mask is formed. P-type channel stop regions and p-type surface channel regions are then formed. A dielectric layer is formed over the surface channel regions. Source regions are formed within the well regions. Drain regions are formed within the drain well regions. Back gate regions are formed within the well regions. Top gates are formed on the dielectric layer overlying the surface channel regions.
    Type: Application
    Filed: June 28, 2005
    Publication date: December 28, 2006
    Inventors: Steven Merchant, Philip Hower, Scott Paiva
  • Publication number: 20050285157
    Abstract: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.
    Type: Application
    Filed: June 23, 2004
    Publication date: December 29, 2005
    Inventors: Philip Hower, David Walch, John Lin, Steven Merchant
  • Publication number: 20050255655
    Abstract: An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.
    Type: Application
    Filed: July 12, 2005
    Publication date: November 17, 2005
    Inventors: Philip Hower, Taylor Efland
  • Publication number: 20050012148
    Abstract: Segmented transistor devices are provided, wherein contiguous individual transistor segments extend along corresponding segment axes, in which two or more of the segment axes are at a non-zero angle with respect to one another. The segmentation of the transistor provides a high overall device aspect ratio which may be easily fit into pre-existing circuit blocks or cells in a device layout, thereby facilitating device scaling.
    Type: Application
    Filed: July 15, 2003
    Publication date: January 20, 2005
    Inventors: Philip Hower, John Lin, Sameer Pendharkar, Steven Jensen