Abstract: An elevator position determination system for determining the position of an elevator car disposed in the elevator hoistway includes a transceiver disposed on the elevator car for generating a query signal and a transponder disposed in the elevator hoistway for providing an identification signal in response to the query signal, wherein, the elevator position determination system determines the elevator car position in response to the identification signal.

Abstract: An emitter and a plurality of sensors and are used to detect the relative positions between an elevator platform and landing sill. The emitters radiate energy through a reflection duct formed between the elevator platform and the landing sill. The plurality of sensors monitor the reflection duct so that radiated energy is detected. The sensors provide level signals in response to the radiated energy. A means responsive to the level signals determines when the platform is level with respect to the landing sill.

Abstract: The pseudorandom process iteratively applies a selected CRC encryption process on the information to be encrypted. The encryption process is selected by testing one of the digits comprising the number to be encrypted. A first encryption process is used if the tested digit is a 1; a second encryption process is used if the tested digit is a 0. The process is repeated a plurality of times, e.g. once for each digit in the number to be encrypted, resulting in a highly encrypted value that is not easily reverse engineered by chosen or known plaintext attack.

Abstract: The pseudorandom process iteratively applies a selected CRC encryption process on the information to be encrypted. The encryption process is selected by testing one of the digits comprising the number to be encrypted. A first encryption process is used if the tested digit is a 1; a second encryption process is used if the tested digit is a 0. The process is repeated a plurality of times, e.g. once for each digit in the number to be encrypted, resulting in a highly encrypted value that is not easily reverse engineered by chosen or known plaintext attack.

Abstract: The first and second devices exchange randomly generated messages that are used in a composition-based encryption/decryption process. At least one of the randomly generated messages is, itself, encrypted before transmission. The composition-based process (a cyclic redundancy code process, preferably enhanced with midcycle non-Galois Field operation) is embedded in both devices and not readily discernable by playback attack.

Abstract: If a transceiver has a message to send during an idle medium condition, it transmits a jam pattern onto the medium for a predetermined time (based on maximum network propagation delay). If a transceiver detects a jamming pattern, it inhibits its own transmissions and waits for the next slot progression. If multiple transceivers begin jamming within a propagation delay of each other (within the network vulnerable time), their jamming transmissions will not destructively interfere with each other. When jamming ceases, all transceivers begin a slot progression. Thus, the end of the jamming period when all transceivers have finished jamming serves as a network-wide synchronization for the start of an implicit token slot progression.

Abstract: Primary implicit token slots (that is, token slots following a message or jam used to restart network activity) are assigned to multiple transceivers. When a transceiver assigned to a shared slot has data to transmit, it emits a jamming signal instead of a message in its token slot. This jamming signal serves as a synchronization for a second implicit token slot progression in which only transceivers sharing the primary level implicit token slot participate.

Abstract: If a transceiver has a message to send during an idle medium condition, it transmits a jam pattern onto the medium for a predetermined time (based on maximum network propagation delay). If a transceiver detects a jamming pattern, it inhibits its own transmissions and waits for the end of the jamming pattern. If multiple transceivers begin jamming within a propagation delay of each other (within the network vulnerable time), their jamming transmissions will not destructively interfere with each other. When jamming ceases, all transceivers begin a time slice progression. Thus, the end of the jamming period when all transceivers have finished jamming serves as a network-wide synchronization for the start of an implicit token time slice progression.

Abstract: The digital information is encrypted by first performing a preselected number of CRC iterations or partial convolutions by multiplication with a mask in the Galois Field. Before the CRC operation is completed, the intermediate resultant is subjected to an Integer Ring operation, such as addition, which injects a nonlinearity over the Galois Field due to possible arithmetic carry operations. After the Integer Ring operation, the Galois Field CRC process is continued to completion. The result is an encrypted value which is not readily decrypted by Galois Field techniques.

Abstract: An automobile door lock receiver module (30) and a plurality of keychain fob transmitter units (16) contain identification numbers, secret initial values, and secret feedback masks so as to authenticate encrypted messages from any of the assigned fobs, indicative of commands registered by closing switches on the fob. Each fob is synchronized with the receiving module by means of a truly random number concatenated with a secret initial value and encrypted, through a linear feedback shift register or other operations. A second secret initial value is encrypted and command bits are exclusive ORed into the low order bit positions; the two encrypted numbers are concatenated and encrypted to form a key word which is transmitted with the fob ID. Synchronization includes decrypting to recover the truly random number and the secret initial value concatenated therewith; the truly random number is compared with previously received random numbers in order to avoid copying of recently transmitted synchronization commands.

Abstract: An automobile door lock receiver module (30) and a plurality of keychain fob transmitter units (16) contain identification numbers, secret initial values, and secret feedback masks so as to authenticate encrypted messages from any of the assigned fobs, indicative of commands registered by closing switches on the fob. Each fob is synchronized with the receiving module by means of a truly random number concatenated with a secret initial value and encrypted, through a linear feedback shift register or other operations. A second secret initial value is encrypted and command bits are exclusive ORed into the low order bit positions; the two encrypted numbers are concatenated and encrypted to form a key word which is transmitted with the fob ID. Synchronization includes decrypting to recover the truly random number and the secret initial value concatenated therewith; the truly random number is compared with previously received random numbers in order to avoid copying of recently transmitted synchronization commands.

Abstract: A computer is provided as an add-on processor for attachment to a host computer. Included are a single data bus, a 32-bit arithmetic logic unit, a data stack, a return stack, a main program memory, data registers, program memory addressing logic, micro-program memory, and a micro-instruction register. Each machine instruction contains an opcode as well as a next address field and subroutine call/return or unconditional branching information. The return address stack, memory addressing logic, program memory, and microcoded control logic are separated from the data bus to provide simultaneous data operations with program control flow processing and instruction fetching and decoding. Subroutine calls, subroutine returns, and unconditional branches are processed with a zero execution time cost. Program memory may be written as either bytes or full words without read/modify/write operations.

Abstract: A computer is provided as an add-on board for attachment to a host computer. Included are a single data bus, a 16-bit arithmetic logic unit, a data stack, a return stack, a main program memory, data registers, program counters, microprocessor memory, and microinstruction register. Each stack has a pointer which may be set without altering the contents of the respective stacks. The main program memory has a direct connection to the writable microprogram memory for providing instruction. MVP-FORTH is used for programming a microcode assembler, a cross-compiler, a set of diagnostic programs, and microcode.