Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).

Abstract: A CMOS receiver system having a tunable receiver having a tunable gain and a bandwidth system is provided. The tunable receiver includes means for receiving input signals; and a control circuit controlled by a control signal for tuning at least one of the gain and the bandwidth of the tunable receiver, wherein the control signal is indicative of a data rate of the input signals. Furthermore, a method is provided for tuning a CMOS receiver receiving input signals. The method includes the steps of receiving at least one control signal, and controlling one of gain and bandwidth of the CMOS receiver in accordance with the at least one control signal, wherein the at least one control signal is indicative of a data rate of the received input signals.

Abstract: A data receiver is provided which includes a front end interface circuit having an alternating current (AC) transmission receiving mode and a direct current (DC) transmission receiving mode. The front end interface circuit includes an offset compensation circuit operable to compensate a DC voltage offset between a pair of differential signals input to the data receiver. The front end interface circuit further includes an AC/DC selection unit operable to switch between (a) the DC transmission receiving mode, and (b) the AC transmission receiving mode, such that the data receiver is operable in (i) the DC transmission mode in which the offset compensation circuit is disabled, (ii) the DC transmission mode in which the offset compensation circuit is enabled, (iii) the AC transmission mode in which the offset compensation circuit is disabled, and (iv) the AC transmission receiving mode in which the offset compensation circuit is enabled.

Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).

Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).

Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).

Abstract: A CMOS receiver system having a tunable receiver having a tunable gain and a bandwidth system is provided. The tunable receiver includes means for receiving input signals; and a control circuit controlled by a control signal for tuning at least one of the gain and the bandwidth of the tunable receiver, wherein the control signal is indicative of a data rate of the input signals. Furthermore, a method is provided for tuning a CMOS receiver receiving input signals. The method includes the steps of receiving at least one control signal, and controlling one of gain and bandwidth of the CMOS receiver in accordance with the at least one control signal, wherein the at least one control signal is indicative of a data rate of the received input signals.

Abstract: An asynchronous serial data receiver utilizes plural samples of each data bit in a word to assure detection and reading of the midpoint of each bit to mitigate problems associated with noise and mismatches between the data and sampling rates. To this end, a shift register having plural stages for each bit samples the data stream at a clock rate which is a multiple of the data rate which provides multiple samples of each incoming bit. When the data word is fully read into the shift register the start bit is detected and initiates a parallel transfer of the data word using bit values taken from the midpoint of each bit period.

Abstract: An asynchronous serial data receiver for receiving a stream of data bits, characterized by a plurality of shift registers (54) into which samples corresponding to points within said data bit stream are read, different shift registers (54) holding a different set of said samples, said points being separated by most one half of a data bit period, and a decoder (60-90) responsive to said samples held in said shift registers (54) for recognizing points of known phase within said data assessed relative to which samples which corresponding to points within said data bits may be identified for reading. The invention provides a high speed serial receiver which is particularly suitable for use within disc drives and data storage and retrieval systems in general. The serial data receiver of the present invention does not require a clock synchronized with the incoming data.