Patents by Inventor Philip J. Rogers

Philip J. Rogers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120194528
    Abstract: Embodiments of the present invention provide a method of preempting a task. The method includes removing the task from the parallel processors via a scheduling mechanism. Responsive to the removing, the method also includes ceasing (i) retrieval of commands from a buffer associated with the task, (ii) dispatch of groups of work-items associated with the task, (iii) dispatch of wavefronts associated with the task, and (iiii) execution of the wavefronts. State information related to the task is saved.
    Type: Application
    Filed: November 30, 2011
    Publication date: August 2, 2012
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Sebastien Nussbaum, Rex McCrary, Mark Leather, Philip J. Rogers, Thomas R. Woller, Kevin McGrath, Nuwan Jayasena
  • Publication number: 20120194527
    Abstract: Embodiments described herein provide a method of arbitrating a processing resource. The method includes receiving a command to preempt a task and preventing additional wavefronts associated with the task from being processed.
    Type: Application
    Filed: November 30, 2011
    Publication date: August 2, 2012
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Sebastien Nussbaum, Rex McCrary, Mark Leather, Philip J. Rogers, Thomas R. Woller
  • Publication number: 20120194525
    Abstract: Provided herein is a method including receiving a run list including one or more processes to run on an accelerated processing device, wherein each of the one or more processes is associated with a corresponding independent job command queue. The method also includes scheduling each of the one or more processes to run on the accelerated processing device based on a criteria associated with each process.
    Type: Application
    Filed: November 23, 2011
    Publication date: August 2, 2012
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Thomas R. Woller, Kevin McGrath, Sebastien Nussbaum, Nuwan Jayasena, Rex McCrary, Philip J. Rogers, Mark Leather
  • Publication number: 20120198458
    Abstract: Embodiments of the present invention provide a method of synchronous operation of a first processing device and a second processing device. The method includes executing a process on the first processing device, responsive to a determination that execution of the process on the first device has reached a serial-parallel boundary, passing an execution thread of the process from the first processing device to the second processing device, and executing the process on the second processing device.
    Type: Application
    Filed: November 30, 2011
    Publication date: August 2, 2012
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Sebastien Nussbaum, Rex McCrary, Mark Leather, Nuwan S. Jayasena, Kevin McGrath, Philip j. Rogers, Thomas Woller
  • Publication number: 20120188258
    Abstract: A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.
    Type: Application
    Filed: November 4, 2011
    Publication date: July 26, 2012
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Rex MCCRARY, Michael Houston, Philip J. Rogers, Gongxian Jeffrey Cheng, Mark Hummel, Paul Blinzer
  • Patent number: 8212832
    Abstract: An apparatus and method utilizes system memory as backing stores so that local graphics memory may be oversubscribed. Surfaces may be paged in and out of system memory based on the amount of usage of the surfaces. The apparatus and method also prioritizes surfaces among different tiers of local memory (e.g. frame buffer), non-local memory (e.g. page locked system memory), and system memory backing stores (e.g. pageable system memory) locations based on predefined criteria and runtime statistics relating to the surfaces. As such, local memory may be, for example, expanded without extra memory costs such as adding a frame buffer memory to allow graphics applications to effectively use more memory and run faster.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: July 3, 2012
    Assignee: ATI Technologies ULC
    Inventors: Steve Stefanidis, Jeffrey G. Cheng, Philip J. Rogers
  • Publication number: 20120147015
    Abstract: A method, computer program product, and computing system are provided for processing a graphics operation. For instance, the method can include receiving the graphics operation from an application. The method can also include allocating a first portion of the graphics operation to a first processing unit and a second portion of the graphics operation to a second processing unit. This allocation between the first and second processing units can be based on at least one of a performance profile and a functionality profile of the first and second processing units.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 14, 2012
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Philip J. Rogers, David A. Gotwalt
  • Publication number: 20120139930
    Abstract: A method of processing commands is provided. The method includes holding commands in queues and executing the commands in an order based on their respective priority. Commands having the same priority are held in the same queue.
    Type: Application
    Filed: June 29, 2011
    Publication date: June 7, 2012
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Philip J. Rogers, David Gotwalt, Tom Frisinger, Rex McCrary
  • Publication number: 20120066444
    Abstract: A method, computer program product, and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method can include associating a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels. Similarly, the method can include associating a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels. The method can also include associating a first sequence identifier and a second sequence identifier with the first memory buffer and the second memory buffer, respectively. Further, the method can include accessing the first and second memory buffers based on the first and second sequence identifiers.
    Type: Application
    Filed: September 14, 2010
    Publication date: March 15, 2012
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Greg SADOWSKI, Philip J. Rogers
  • Publication number: 20120066471
    Abstract: A method and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method and apparatus associates one or more memory buffers with a plurality of memory banks based on preferred performance settings, wherein the plurality of memory banks spans over one or more of the plurality of memory channels. Additionally, the method and apparatus accesses the one or more memory buffers based on the preferred performance settings. Further, the method and apparatus can, in response to accessing the one or more memory buffers based on the preferred performance settings, determine whether the preferred performance settings are being satisfied.
    Type: Application
    Filed: November 22, 2011
    Publication date: March 15, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Greg Sadowski, Philip J. Rogers, John Wakefield Brothers, III, W. Fritz Kruger, Konstantine I. Iourcha
  • Publication number: 20110060879
    Abstract: A processing system is provided. The processing system includes a first processing unit coupled to a first memory and a second processing unit coupled to a second memory. The second memory comprises a coherent memory and a private memory that is private to the second processing unit.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 10, 2011
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Philip J. ROGERS, Warren Fritz Kruger, Mark Hummel, Eric Demers
  • Publication number: 20110057939
    Abstract: Disclosed herein are systems, apparatuses, and methods for enabling efficient reads to a local memory of a processing unit. In an embodiment, a processing unit includes an interface and a buffer. The interface is configured to (i) send a request for a portion of data in a region of a local memory of an other processing unit and (ii) receive, responsive to the request, all the data from the region. The buffer is configured to store the data from the region of the local memory of the other processing unit.
    Type: Application
    Filed: March 8, 2010
    Publication date: March 10, 2011
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: David I.J. GLEN, Philip J. Rogers, Gordon F. Caruk, Gongxian Jeffrey Cheng, Mark Hummel, Stephen Patrick Thompson, Anthony Asaro
  • Patent number: 7663635
    Abstract: A system and method for memory mapping in a multiple video processor (multi VPU) system is described. In various embodiments, rendering tasks are shared among multiple VPUs in parallel to provide improved performance and capability with minimal increased cost. In various embodiments, multiple VPUs in a system access each other's local memories to facilitate cooperative video processing. In one embodiment, each VPU in the system has the local memories of each other VPU mapped to its own graphics aperture relocation table (GART) table to facilitate access via a virtual addressing scheme. Each VPU uses the same virtual addresses for this mapping to other VPU local memories. This allows the driver to send exactly the same write commands to each VPU, including the numeric value of the destination address for operations such as writing rendered data. Thus, unique addresses need not be generated for each VPU.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: February 16, 2010
    Assignee: ATI Technologies, Inc.
    Inventors: Philip J. Rogers, Jeffrey Gongxian Cheng, Dmitry Semiannikov, Raja Koduri
  • Patent number: 6975325
    Abstract: A method and apparatus for graphics processing using state and shader management includes at least one state and shader cache coupled to a compiler for compiling a hardware state and shader vector from an abstract state vector. Also included is an abstract state vector register containing the abstract state vector that is provided to the state and shader cache and the compiler. The state and shader cache receives the abstract state vector and determines whether a cache entry for that abstract state vector already exists. If the cache entry exists, the hardware state and shader vector is provided to hardware. If the entry does not exist, the state and shader cache provides a miss signal to the compiler, whereupon the compiler compiles the abstract state vector and generates a hardware state and shader vector. Thereupon the hardware state and shader vector is provided to the hardware.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: December 13, 2005
    Assignee: ATI Technologies Inc.
    Inventors: Stephen L. Morein, Tom E. Frisinger, Philip J. Rogers, Richard Bagley
  • Patent number: 6778178
    Abstract: A graphic accelerator interface device for a computer is provided. The accelerator has a host data path that includes a plurality of comparators, each assigned to permit os/application access to a different “surface” which is defined by an address range corresponding to a block of data in a frame buffer. Unlike the prior art, an access flag register is associated with the host data path such that each surface assigned to a comparator has associated read and write flags. Whenever a read or a write occurs to one of the assigned surfaces via the host data path, the corresponding flag is set. Preferably, for os/application access, the surfaces contain data in an untiled format which the graphic accelerator uses in a tiled format. The invention affords more efficient, i.e.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: August 17, 2004
    Assignee: ATI International, SRL
    Inventors: Indra Laksono, David I. J. Glen, Philip J. Rogers, Anthony D. Scarpino
  • Publication number: 20040145814
    Abstract: An optical device adapted for handling plane polarised light comprising a beamsplitter cube formed of two prisms having a polarising beamsplitter (PBS) arrangement located between the hypoteneuse faces of the prisms, the cube having a first pair of opposing faces forming an illumination input face and an illumination output face, and a second pair of opposing faces at which reflection means are located, wherein image-forming light is output from the output face, the image being derived from a display source located at one of the other faces of the cube and the arrangement of the reflection means being such that the cube does not support an intermediate image of the display source.
    Type: Application
    Filed: October 30, 2003
    Publication date: July 29, 2004
    Inventor: Philip J Rogers
  • Patent number: 6704021
    Abstract: A video graphics system (300) employs a method and apparatus for efficiently processing vertex information required to render graphics primitives requested for display by an application (313), such as a video game. The video graphics system includes a graphics driver (317), a graphics processor (305), a memory component (309, 321) that is accessible by the graphics processor, and a memory component (319) that is inaccessible by the graphics processor. After receiving, from the application, a drawing command that includes vertex indices and a reference to a vertex buffer (325) stored in the graphics processor-inaccessible memory component, the graphics driver allocates a new temporary vertex buffer (327) in the graphics processor-accessible memory component and copies the contents of the graphics processor-inaccessible vertex buffer into the temporary vertex buffer.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: March 9, 2004
    Assignee: ATI International SRL
    Inventors: Philip J. Rogers, Matthew P. Radecki
  • Patent number: 6331854
    Abstract: A method and apparatus for accelerating animation in a video graphics system is accomplished by storing drawing operations for a first scene in a bus master buffer. The first scene is to be drawn to a first frame. A frame flip operation is then stored in the bus master buffer at a location subsequent to the drawing operations for the first scene such that when accessed by a graphics processor, the frame flip will be performed after the drawing operations for the first scene have completed. Drawing calculations for a second scene to be drawn to a second frame are performed, and the resulting drawing operations are stored in the bus master buffer at a location subsequent to the page flip operation. The graphics processor is signaled, and the graphics processor fetches and executes the commands in the bus master buffer sequentially such that the drawing operations to the first frame are performed first, followed by the frame flip operation and finally the drawing operations to the second frame.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: December 18, 2001
    Assignee: Azi International SRL
    Inventors: Philip J. Rogers, Xiaoqing Wu
  • Patent number: 6201547
    Abstract: A method and apparatus for sequencing texture updates in a video graphics system is accomplished by storing a first portion of graphics data in a first position of a bus master buffer, where the first portion of the graphics data utilizes a texture. An indication of a texture update is then received, where the texture update, when performed, modifies the texture to produce an updated texture that is used by subsequent graphics data. The updated texture is stored in a second position of the bus master buffer. A second portion of the graphics data, which utilizes the updated texture, is then stored in a third position of the bus master buffer. The data in the bus master buffer is then accessed through a direct memory access transfer initiated by the graphics processor in the system. The bus master buffer data is accessed in a sequential manner, which ensures that the texture update does not occur until after the graphics data utilizing the original texture has been drawn.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: March 13, 2001
    Assignee: ATI International SRL
    Inventors: Philip J. Rogers, Xiaoqing Wu
  • Patent number: 6166724
    Abstract: A method and apparatus for sequencing palette updates in a video graphics system is accomplished by first storing a first portion of graphics data in a first position of a bus master buffer, where the first portion of the graphics data utilizes a palette. An indication of a palette update is then received, where the palette update will be used by subsequent graphics data. The updated palette is stored in a second position of the bus master buffer. A second portion of the graphics data, which utilizes the updated palette, is then stored in a third position of the bus master buffer. The data in the bus master buffer is then fetched through a direct memory access transfer initiated by the graphics processor in the system. The data is fetched in a sequential manner, which ensures that the palette update does not occur until after the graphics data utilizing the original palette has been drawn.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: December 26, 2000
    Assignee: ATI International SRL
    Inventors: Jeffrey D. Paquette, Philip J. Rogers