Patents by Inventor Philip J. Stringer

Philip J. Stringer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for the automatic generation of boundary scan description language files
    Patent number: 5682392
    Abstract: A method and apparatus is presented for the automatic generation of boundary scan description language files for integrated circuits incorporating boundary scan circuitry of indeterminate configuration. The user enters basic pin information for the integrated circuit under consideration, along with an identification of which pins are the boundary-scan TAP pins and which are the power and ground pins. The user connects the pins of a sample integrated circuit to the test channels of the apparatus of the invention.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: October 28, 1997
    Assignee: Teradyne, Inc.
    Inventors: Douglas W. Raymond, D. Eugene Wedge, Philip J. Stringer
  • Manufacturing defect analyzer
    Patent number: 5554928
    Abstract: A method for detecting faults on a printed circuit board populated with semiconductor electronic components. To detect faults, signal pins on the components are taken in pairs. The an indication of the common mode resistance between those pins and ground is computed from a series of current measurements. An error is detected when the common mode resistance is outside of a predetermined range. A "learn mode" is also disclosed in which the pairs of leads used for the test are selected by taking measurements on a known good board without detailed knowledge of the semiconductor components on the board.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: September 10, 1996
    Assignee: Teradyne, Inc.
    Inventor: Philip J. Stringer
  • Manufacturing defect analyzer
    Patent number: 5521513
    Abstract: A method for detecting faults on a printed circuit board populated with semiconductor electronic components. To detect faults, signal pins on the components are taken in pairs. The an indication of the common mode resistance between those pins and ground is computed from a series of current measurements. An error is detected when the common mode resistance is outside of a predetermined range. A "learn mode" is also disclosed in which the pairs of leads used for the test are selected by taking measurements on a known good board without detailed knowledge of the semiconductor components on the board.
    Type: Grant
    Filed: October 25, 1994
    Date of Patent: May 28, 1996
    Inventor: Philip J. Stringer
  • Microprocessor timing emulator having a "Wait" state
    Patent number: 4785416
    Abstract: Within a test system for testing microprocessor-based systems, an apparatus for emulating the timing characteristics of a microprocessor, including when the microprocessor goes to a "WAIT" state during the execution of an instruction cycle. A control signal RAM has a plurality of sets of instructions, each set being stored in a specific region, each set corresponding to the timing characteristics, that is the control, address and data signals, of a microprocessor. A decode RAM stores coded instructions for addressing each region of the control signal RAM. A sequence control RAM contains data for addressing each address location in the region of the control signal RAM selected by a signal input to the decode RAM.
    Type: Grant
    Filed: March 16, 1987
    Date of Patent: November 15, 1988
    Inventor: Philip J. Stringer