Patents by Inventor Philip J. Yearsley
Philip J. Yearsley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5617298Abstract: A collinear terminated transmission line structure and method for producing same is presented. The structure comprises a plurality of conductors electrically connected to a plurality of resistors. A predetermined spacing between each of the plurality of conductors ranges from 2 mils to 7 mils. Greater spacings are easily accomplished with the present method. The method comprises the steps of screen-printing a resistor swath onto a substrate, the swath being adjacent to one end of the plurality of conductors. After the substrate is dipped into a solution, the resistor swath is laser trimmed to form the plurality of resistors. The substrate is then rinsed with warm water to remove the solution. The solution can be a poly-vinyl alcohol and isopropyl alcohol mixture.Type: GrantFiled: December 20, 1995Date of Patent: April 1, 1997Assignee: Hewlett-Packard CompanyInventors: John F. Casey, Ronald W. Schroeder, Lewis R. Dove, Philip J. Yearsley
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Patent number: 5602483Abstract: An electronic probe circuit having ac and dc amplifiers and an input compensation subcircuit is enclosed within a trim housing that replicates the electrical effect of the probe housing. The circuit is laser trimmed through ports in the trim housing. The difference between the voltage at 80 nsec and 1.4 .mu.sec points on a step voltage provides a first calibration factor while the difference between the 3 nsec voltage and the 80 nsec voltage provides a second calibration factor. A resistor in the DC amplifier is trimmed to an absolute voltage with a step scan laser cut. A resistor in the AC amplifier is trimmed with a laser L-cut until the difference between the 80 nsec and 1.4 .mu.sec points of the step voltage equals the first calibration factor. A capacitor in the input compensation subcircuit is trimmed until the voltage difference between the 3 nsec and 80 nsec points equals the second calibration factor.Type: GrantFiled: February 27, 1995Date of Patent: February 11, 1997Assignee: Hewlett-Packard CompanyInventors: Thomas F. Uhling, Philip J. Yearsley, Dale L. Pittock, Mark E. Mathews
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Patent number: 5525910Abstract: An electronic probe circuit having ac and dc amplifiers and an input compensation subcircuit is enclosed within a trim housing that replicates the electrical effect of the probe housing. The circuit is laser trimmed through ports in the trim housing. The difference between the voltage at 80 nsec and 1.4 .mu.sec points on a step voltage provides a first calibration factor while the difference between the 3 nsec voltage and the 80 nsec voltage provides a second calibration factor. A resistor in the DC amplifier is trimmed to an absolute voltage with a step scan laser cut. A resistor in the AC amplifier is trimmed with a laser L-cut until the difference between the 80 nsec and 1.4 .mu.sec points of the step voltage equals the first calibration factor. A capacitor in the input compensation subcircuit is trimmed until the voltage difference between the 3 nsec and 80 nsec points equals the second calibration factor.Type: GrantFiled: March 2, 1995Date of Patent: June 11, 1996Assignee: Hewlett-Packard CompanyInventors: Thomas F. Uhling, Philip J. Yearsley, Dale L. Pittock, Mark E. Mathews
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Patent number: 5504986Abstract: A collinear terminated transmission line structure and method for producing same is presented. The structure comprises a plurality of conductors electrically connected to a plurality of resistors. A predetermined spacing between each of the plurality of conductors ranges from 2 mils to 7 mils. Greater spacings are easily accomplished with the present method. The method comprises the steps of screen-printing a resistor swath onto a substrate, the swath being adjacent to one end of the plurality of conductors. After the substrate is dipped into a solution, the resistor swath is laser trimmed to form the plurality of resistors. The substrate is then rinsed with warm water to remove the solution. The solution can be a poly-vinyl alcohol and isopropyl alcohol mixture.Type: GrantFiled: March 2, 1995Date of Patent: April 9, 1996Assignee: Hewlett-Packard CompanyInventors: John F. Casey, Ronald W. Schroeder, Lewis R. Dove, Philip J. Yearsley
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Patent number: 5446260Abstract: An electronic probe circuit having ac and dc amplifiers and an input compensation subcircuit is enclosed within a trim housing that replicates the electrical effect of the probe housing. The circuit is laser trimmed through ports in the trim housing. The difference between the voltage at 80 nsec and 1.4 .mu.sec points on a step voltage provides a first calibration factor while the difference between the 3 nsec voltage and the 80 nsec voltage provides a second calibration factor. A resistor in the DC amplifier is trimmed to an absolute voltage with a step scan laser cut. A resistor in the AC amplifier is trimmed with a laser L-cut until the difference between the 80 nsec and 1.4 .mu.sec points of the step voltage equals the first calibration factor. A capacitor in the input compensation subcircuit is trimmed until the voltage difference between the 3 nsec and 80 nsec points equals the second calibration factor.Type: GrantFiled: January 18, 1994Date of Patent: August 29, 1995Assignee: Hewlett-Packard CompanyInventors: Thomas F. Uhling, Philip J. Yearsley, Dale L. Pittock, Mark E. Mathews
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Patent number: 5428204Abstract: An electronic probe circuit having ac and dc amplifiers and an input compensation subcircuit is enclosed within a trim housing that replicates the electrical effect of the probe housing. The circuit is laser trimmed through ports in the trim housing. The difference between the voltage at 80 nsec and 1.4 .mu.sec points on a step voltage provides a first calibration factor while the difference between the 3 nsec voltage and the 80 nsec voltage provides a second calibration factor. A resistor in the DC amplifier is trimmed to an absolute voltage with a step scan laser cut. A resistor in the AC amplifier is trimmed with a laser L-cut until the difference between the 80 nsec and 1.4 .mu.sec points of the step voltage equals the first calibration factor. A capacitor in the input compensation subcircuit is trimmed until the voltage difference between the 3 nsec and 80 nsec points equals the second calibration factor.Type: GrantFiled: January 18, 1994Date of Patent: June 27, 1995Assignee: Hewlett-Packard CompanyInventors: Thomas F. Uhling, Philip J. Yearsley, Dale L. Pittock, Mark E. Mathews
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Patent number: 5420515Abstract: An electronic probe circuit having ac and dc amplifiers and an input compensation subcircuit is enclosed within a trim housing that replicates the electrical effect of the probe housing. The circuit is laser trimmed through ports in the trim housing. The difference between the voltage at 80 nsec and 1.4 .mu.sec points on a step voltage provides a first calibration factor while the difference between the 3 nsec voltage and the 80 nsec voltage provides a second calibration factor. A resistor in the DC amplifier is trimmed to an absolute voltage with a step scan laser cut. A resistor in the AC amplifier is trimmed with a laser L-cut until the difference between the 80 nsec and 1.4 .mu.sec points of the step voltage equals the first calibration factor. A capacitor in the input compensation subcircuit is trimmed until the voltage difference between the 3 nsec and 80 nsec points equals the second calibration factor.Type: GrantFiled: August 28, 1992Date of Patent: May 30, 1995Assignee: Hewlett-Packard CompanyInventors: Thomas F. Uhling, Philip J. Yearsley, Dale L. Pittock, Mark E. Mathews