Abstract: An EEPROM cell that combines a FET transistor and a capacitor. The transistor has a well that is shared by potentially all of the EEPROM cells in the array thereby reducing size. A gate terminal is formed over the well. Source and drain terminals are formed in the well. The well is isolated from the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal, and may be oppositely doped from the gate terminal to improve retention. The second terminal is formed by a second well that is underneath the first terminal and isolated from the first terminal. The capacitance may be increased without area increase by forming a metal layer over the first terminal and separated from the first terminal by a thick dielectric layer, and connected to the second well via a conductive via.

Abstract: A liquid crystal on silicon (LCOS) display pixel with dual storage capacitors for increasing the storage capacitance of the charge storage node for the liquid crystal pixel. The two capacitors are in a stacked arrangement. The bottom capacitor is formed by using a buried diffusion layer as the bottom electrode, a first layer of polysilicon (poly) as the top electrode and silicon dioxide as the dielectric. The top capacitor is a poly-to-poly capacitor formed by using the first layer of poly as the bottom electrode and a second layer of poly as the top electrode.

Abstract: A pixel cell array for a reflective silicon light valve features a planar surface alignment layer of uniform thickness over the active pixel electrodes. The surface alignment layer is formed by flowing and curing multiple quantities of alignment material. A first quantity of low viscosity alignment material is spun over the surface and settles into trenches between the raised active pixel electrodes. Curing of the first quantity of alignment material forms a lower alignment layer in the trenches, reducing topography offered by the array surface. A second, larger quantity of higher viscosity alignment material is then spun over active pixel electrodes and the lower alignment layer. The second quantity of alignment material is then cured to form a surface alignment layer. Because of reduction in topography of the array surface by the lower alignment layer, the surface alignment layer is both substantially planar and of uniform thickness across the surface of the active pixel electrode.

Abstract: A process flow for forming a pixel cell for a light valve implements the furnace alloy/sintering step prior to deposition of the reflective metal layer from which the active pixel electrodes are to be formed. In this manner, the active pixel electrodes are spared loss of reflectance associated with prolonged exposure to high temperatures of the furnace alloy/sintering step. Adequate suppression of surface state charges created after the furnace alloy/sintering is ensured by performing a rapid thermal anneal at the conclusion of the process flow.

Abstract: An EEPROM cell is formed in an IC chip by using only three masking steps in addition to those required for the basic CMOS transistors in the chip. A first mask layer is used to define source/drain regions of select and memory transistors within the EEPROM cell; a second mask layer is used to define a tunneling region of the memory transistor; and a third mask layer is used to define a floating gate of the memory transistor and a gate of the select transistor. A control gate of the memory transistor is formed using the same mask that is used to define the gates of the CMOS transistors. The third and fourth mask layers may also be used to form the lower and upper electrodes, respectively, of a capacitor.