Patents by Inventor Philip John Crawley
Philip John Crawley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230008422Abstract: A planar inductor may include a first coil and a second coil. The first coil may include a first trace that forms a first set of turns. The second coil may include a second trace that forms a second set of turns. A distance between the turns of the first set of turns may be equal to a distance between the turns of the second set of turns. A width of the first trace may be equal to a width of the second trace. The first coil and the second coil may be physically positioned or sized according to a/b in which a represents the width of the first trace and b represents the distance between the turns of the first set of turns.Type: ApplicationFiled: July 8, 2022Publication date: January 12, 2023Applicant: SMART PRONG TECHNOLOGIES, INC.Inventors: Philip John CRAWLEY, Stephen W. ELLSWORTH
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Patent number: 9197423Abstract: A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device. First and second resistors are respectively coupled to the differential lines between the integrated active common mode suppression and electrostatic discharge protection circuit and the electronic device.Type: GrantFiled: February 14, 2008Date of Patent: November 24, 2015Assignee: AKROS SILICON, INC.Inventors: Philip John Crawley, Amit Gattani, John R. Camagna, Jun Cai
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Patent number: 9189036Abstract: In a network device, a connector module comprises a network connector coupled to the connector module in a configuration that transfers power and communication signals and an application connector that comprises serial media independent interface (SMII) pins and power pins. A Power-over-Ethernet (PoE) circuit is coupled between the network connector and the application connector.Type: GrantFiled: April 24, 2007Date of Patent: November 17, 2015Assignee: AKROS SILICON, INC.Inventors: Sajol Ghoshal, John R. Camagna, Philip John Crawley
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Patent number: 9185834Abstract: A network device comprises an Ethernet physical layer (PHY) comprising an isolation, protection, and electromagnetic interference suppression barrier operative for isolated power and data transfer.Type: GrantFiled: April 24, 2007Date of Patent: November 10, 2015Assignee: AKROS SILICON, INC.Inventors: Philip John Crawley, Sajol Ghoshal, John R. Camagna
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Patent number: 8400230Abstract: In an electronic system, a frequency modulator manages clock signals for electromagnetic interference (EMI) reduction. The illustrative frequency modulator comprises a core oscillator, and a clock divider coupled to the core oscillator that modulates frequency of the core oscillator and deterministically spreads clock spectral components of a digital clock signal whereby electromagnetic interference (EMI) is reduced. The frequency modulator further comprises a circuit coupled to the clock divider that receives the digital clock signal, combines the digital clock signal with a data bitstream for transmission across an isolation barrier, and resynchronizes to the digital clock signal.Type: GrantFiled: July 31, 2009Date of Patent: March 19, 2013Assignee: Akros Silicon Inc.Inventors: Philip John Crawley, Kenneth William Taylor
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Patent number: 7965480Abstract: A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device.Type: GrantFiled: November 5, 2007Date of Patent: June 21, 2011Assignee: Akros Silicon Inc.Inventors: Philip John Crawley, Amit Gattani, Jun Cai
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Patent number: 7923710Abstract: A signal isolator comprises an isolation barrier, a transmitter, a differentiator, and a recovery circuit. The transmitter is coupled to a first side of the isolation barrier and is configured to receive and convert an information signal to a differential signal that encodes information in the information signal in a single transition edge. The differentiator is coupled to a second side that is isolated from the first side of the isolation harrier and differentiates the differential signal. The recovery circuit is coupled to the differentiator and operates to recover an output information signal based on the information in the single transition edge.Type: GrantFiled: March 8, 2007Date of Patent: April 12, 2011Assignee: Akros Silicon Inc.Inventors: Philip John Crawley, Sajol Ghoshal, John R. Camagna
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Patent number: 7898825Abstract: A current-mode controller comprises an inductance element, at least one semiconductor switch coupled to the inductance element, and a ramp compensator coupled to sense an indication of current through the inductance element and coupled to control the at least one semiconductor switch that senses current during on-time of the DC-DC converter, infers current during off-time of the DC-DC converter, and determines a slope compensation signal based on the sensed and inferred currents.Type: GrantFiled: March 24, 2008Date of Patent: March 1, 2011Assignee: Akros Silicon, Inc.Inventors: Michael D Mulligan, Philip John Crawley, John Camagna
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Publication number: 20110026655Abstract: In an electronic system, a frequency modulator manages clock signals for electromagnetic interference (EMI) reduction. The illustrative frequency modulator comprises a core oscillator, and a clock divider coupled to the core oscillator that modulates frequency of the core oscillator and deterministically spreads clock spectral components of a digital clock signal whereby electromagnetic interference (EMI) is reduced. The frequency modulator further comprises a circuit coupled to the clock divider that receives the digital clock signal, combines the digital clock signal with a data bitstream for transmission across an isolation barrier, and resynchronizes to the digital clock signal.Type: ApplicationFiled: July 31, 2009Publication date: February 3, 2011Inventors: Philip John Crawley, Kenneth William Taylor
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Publication number: 20100193907Abstract: A semiconductor device comprises an integrated circuit formed on a substrate with a signal interface and at least one isolator capacitor. The integrated circuit comprises a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate, a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics, and a thick metal layer formed on the thick passivation layer. The thick passivation layer has a thickness selected to be greater than the isolation thickness whereby testing for defects is eliminated. The one or more isolator capacitors comprise the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator.Type: ApplicationFiled: April 13, 2010Publication date: August 5, 2010Inventors: Philip John Crawley, Sajol Ghoshal
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Patent number: 7732889Abstract: A semiconductor device comprises an integrated circuit formed on a substrate with a signal interface and at least one isolator capacitor. The integrated circuit comprises a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate, a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics, and a thick metal layer formed on the thick passivation layer. The thick passivation layer has a thickness selected to be greater than the isolation thickness whereby testing for defects is eliminated. The one or more isolator capacitors comprise the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator.Type: GrantFiled: May 24, 2007Date of Patent: June 8, 2010Assignee: Akros Silicon Inc.Inventors: Philip John Crawley, Sajol Ghoshal
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Patent number: 7706112Abstract: An active clamp device electrically couples first and second nodes in respective first and second supply domains referenced to ground potentials that can be different. The active clamp device comprises first and second active devices controlled by signals respectively referenced to the first and second supply domains that create a short-circuit or low impedance connection between the first and second nodes in normal operation and drive impedance between the first and second nodes high in response to a transient event.Type: GrantFiled: December 19, 2006Date of Patent: April 27, 2010Assignee: Akros Silicon Inc.Inventors: Philip John Crawley, Sajol Ghoshal
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Publication number: 20100054001Abstract: A power converter is configured for usage in a power factor correction system. The power converter comprises a transformer with a primary winding and a secondary winding which isolates a primary side from a secondary side. A primary side switch is coupled to the primary winding. An isolator coupled to the primary side switch isolates the primary side from the secondary side and comprises a signal pathway passing a digital signal from the primary side to the secondary side. Power factor correction circuitry is coupled to the primary side switch and adjusts electric load characteristics to improve power factor toward unity.Type: ApplicationFiled: August 26, 2008Publication date: March 4, 2010Inventors: Kenneth Dyer, Sajol Ghoshal, Philip John Crawley, John Camagna
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Publication number: 20090327766Abstract: A power over Ethernet (PoE) system has a reclassification functionality. The illustrative PoE system comprises a powered device (PD) and a power sourcing equipment (PSE) communicatively coupled to the PD. A classification identification component coupled to the PD encodes a classification value. A classification identification component can typically be implemented as a classification resistor, although any other suitable component such as a capacitor, inductor, register, or other structure or method can otherwise be implemented. The PoE system can further comprise a reclassification register in a non-volatile memory that stores a value indicative of a new classification state and a new classification identifier and a power switch that powers the powered device to a classification voltage.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Inventors: Sajol Ghoshal, Abbas Hage, John Camagna, Philip John Crawley
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Publication number: 20090237058Abstract: A current-mode controller comprises an inductance element, at least one semiconductor switch coupled to the inductance element, and a ramp compensator coupled to sense an indication of current through the inductance element and coupled to control the at least one semiconductor switch that senses current during on-time of the DC-DC converter, infers current during off-time of the DC-DC converter, and determines a slope compensation signal based on the sensed and inferred currents.Type: ApplicationFiled: March 24, 2008Publication date: September 24, 2009Inventors: Michael D. Mulligan, Philip John Crawley, John Camagna
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Publication number: 20090207538Abstract: A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device. First and second resistors are respectively coupled to the differential lines between the integrated active common mode suppression and electrostatic discharge protection circuit and the electronic device.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Inventors: Philip John Crawley, Amit Gattani, John R. Camagna, Jun Cai
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Publication number: 20090201115Abstract: An electronic circuit in an integrated circuit package comprises an inductance element. The inductance element further comprises a plurality of separated metal strips formed on a substrate and a ferrite core coupled to the substrate. The metal strip plurality is formed between the substrate and the ferrite core. The inductance element further comprises a plurality of wires coupled to the separated metal strips whereby the metal strips and wires form a continuous coil. The ferrite core is interposed between the metal strip plurality and the wire plurality.Type: ApplicationFiled: February 13, 2008Publication date: August 13, 2009Inventors: Sajol Ghoshal, Philip John Crawley
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Patent number: 7560825Abstract: Embodiments disclosed herein provide a network device comprises a transformer with a primary winding and a secondary winding. The primary winding is coupled to receive input signals from a network connector and supply data signals to a physical layer (PHY) module. An inductance boost circuit is coupled to the secondary winding and operable to increase the impedance of the primary winding. In other embodiments, a network device comprises an autotransformer coupled to receive input signals from a network connector and supply data signals to a physical layer (PHY) module. An electronic load coupled in parallel between the autotransformer and the PHY layer module.Type: GrantFiled: April 11, 2006Date of Patent: July 14, 2009Assignee: Akros Silicon, Inc.Inventor: Philip John Crawley
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Patent number: 7500118Abstract: In a network device, a power potential rectifier is adapted to conductively couple a network connector to an integrated circuit that rectifies and passes a power signal and data signal received from the network connector. The power potential rectifier regulates a received power and/or data signal to ensure proper signal polarity is applied to the integrated circuit.Type: GrantFiled: November 21, 2005Date of Patent: March 3, 2009Assignee: Akros Silicon Inc.Inventors: Philip John Crawley, John R. Camagna
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Publication number: 20080290444Abstract: A semiconductor device comprises an integrated circuit formed on a substrate with a signal interface and at least one isolator capacitor. The integrated circuit comprises a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate, a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics, and a thick metal layer formed on the thick passivation layer. The thick passivation layer has a thickness selected to be greater than the isolation thickness whereby testing for defects is eliminated. The one or more isolator capacitors comprise the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator.Type: ApplicationFiled: May 24, 2007Publication date: November 27, 2008Inventors: Philip John Crawley, Sajol Ghoshal