Abstract: A digital control system for a switch mode power supply (SMPS), the control system having a demand input for a signal indicating whether an output voltage of said SMPS is above or below a desired value, and a drive output for a switch controlling energy transfer between an input and an output of said SMPS during a power switching cycle, the control system further including: a signal processor coupled to said demand input and to said drive output to control said drive output responsive to said demand signal to regulate said output voltage at said desired value, and wherein said signal processor includes at least one storage element to store at least one value of said demand signal, and wherein said switching control signal for a said power switching cycle is responsive to a value of said demand signal in at least two previous power switching cycles.

Abstract: This invention relates to improved control systems and methods for switch mode power supplies.

Abstract: We describe a switch mode power supply (SMPS) controller employing a combination of pulse frequency and pulse width modulation. The controller employs a “gear box” control scheme using two complementary control loops, one for real-time control of the SMPS using PFM and a second using a PWM control scheme which monitors the switching frequency and, at defined operating points, adjusts the pulse width up or down through a set of pre-determined values. This can be considered analogous to the gearbox of a motor vehicle with the SMPS pulse width, switching frequency and output power roughly corresponding to the vehicle's gear ratio, engine speed and road speed respectively.

Abstract: A data communications system memory interface circuit (32) is provided which operates within an adapter circuit (10). Adapter circuit (10) comprises a communications processor (28), a system interface (30) and a protocol handler (20) coupled together by an adapter bus (26). Communications processor (28) accesses an external memory (38) through a memory interface (32). Memory interface (32) comprises a map register circuit (36) which comprises a number of map registers (44 through 56). The map registers (44 through 56) each are operable to store a portion of a twenty bit address which may be selected by a multiplexer (42) responsive to control signals generated by a control logic circuit (40). The address portion stored in the map registers (44 through 56) are added to a remaining portion of an address to form a complete twenty bit remapped address.