Abstract: A code generator, for providing a PRN sequence in a GNSS receiver, has the capability to store an internal status at any given point of the generated sequence. The stored status can be reloaded in the generator, upon an external command, or after a given number of generation cycles, thus slewing the phase of the generated PRN sequence to the value corresponding to the stored status. A parallel-correlation GNSS receiver includes one or more slewable code generators, for successively generating local replicas of GNSS PRN sequences, having different code phases, corresponding to a plurality of candidate signals of different code and Doppler shifts. Each time the code generator must switch from one candidate to a second, it is preemptively controlled or programmed, while generating the code for the first candidate, to store the internal status at the phase point almost aligned with the start of the PRN sequence for the second candidate.

Abstract: A signal processing system and method for a GNSS digital signal wherein a carrier-stripped GNSS signal, is sampled according to a variable rate, determined by the code NCO, and including a timing circuit arranged to generate a timestamp code determining the sampling time of at least one of the samples in the buffer memory. By taking code samples in this way it is possible to transfer the samples asynchronously to a separate processor for the search task to be performed, for example an asynchronous parallel correlator implemented in the same silicon in hardware, or a media processor such as a graphics accelerator implemented in the same device or a separate physical device.

Abstract: A signal processor for GPS or other GNSS radiolocalization systems, includes a RAM pre-correlation buffer which is filled in sync with the code NCO, thus all sample alignment in the buffer is fixed The device further includes an amplitude compressor to limit the size of the buffer memory and is optimized to provide data to the following DFT unit in small bursts that can be processed in real time without the need for intermediate buffers. Thanks to these features the processor limits the amount of fast intermediate memories, is simpler and has lowerpower consumption.

Abstract: A Viterbi decoder which is based on a special instruction set implemented in the processor, enabling it to handle the Viterbi processing with a much lower CPU loading without significantly increasing the hardware complexity. By careful application of appropriate design constraints specific to the SV navigation and analysis of the Viterbi algorithm an optimised architecture can be realized for embedding Viterbi acceleration logic efficiently into a GNSS chipset.

Abstract: A device to perform DFT calculations, for example in a GNSS receiver, including two banks of multipliers by constant integer value, the values representing real and imaginary part of twiddle factors in the DFT. A control unit selectively routes the data through the appropriate multipliers to obtain the desired DFT terms. Unused multipliers are tied to constant input values, in order to minimize dynamic power.

Abstract: A GNSS platform architecture with advanced tracking and search engines. The tracking and search functions are separated into 2 independent engines each highly optimized for their targeted functions.

Abstract: A GPS, GLONASS or Galileo receiver for radio positioning signals wherein at least a part of the computing of position related data based on radio signals received from a plurality of space vehicles is carried out by a graphics or sound processor. The receiver thus makes use of available computing resources, thus achieving a lower bill of material.

Abstract: The invention consists of a barometric pressure sensor, coupled to a processor for recording changes in the pressure over time, this is coupled to a GPS device providing an accurate measurement of the altitude which allows for the barometric pressure measurements to be normalized, typically to mean sea level. Once the measurements have been normalized the effects of the vertical motion of the sensor are effectively removed and the resulting trend shows the absolute atmospheric pressure which can then be used for weather prediction.

Abstract: A device to perform DFT calculations, for example in a GNSS receiver, including two banks of multipliers by constant integer value, the values representing real and imaginary part of twiddle factors in the DFT. A control unit selectively routes the data through the appropriate multipliers to obtain the desired DFT terms. Unused multipliers are tied to constant input values, in order to minimize dynamic power.

Abstract: A Viterbi decoder which is based on a special instruction set implemented in the processor, enabling it to handle the Viterbi processing with a much lower CPU loading without significantly increasing the hardware complexity. By careful application of appropriate design constraints specific to the SV navigation and analysis of the Viterbi algorithm an optimised architecture can be realised for embedding Viterbi acceleration logic efficiently into a GNSS chipset.

Abstract: A GPS, GLONASS or Galileo receiver for radio positioning signals wherein at least a part of the computing of position related data based on radio signals received from a plurality of space vehicles is carried out by a graphics or sound processor. The receiver thus makes use of available computing resources, thus achieving a lower bill of material.

Abstract: A signal processing system and method for a GNSS digital signal wherein a carrier-stripped GNSS signal, is sampled according to a variable rate, determined by the code NCO, and including a timing circuit arranged to generate a timestamp code determining the sampling time of at least one of the samples in the buffer memory. By taking code samples in this way it is possible to transfer the samples asynchronously to a separate processor for the search task to be performed, for example an asynchronous parallel correlator implemented in the same silicon in hardware, or a media processor such as a graphics accelerator implemented in the same device or a separate physical device.

Abstract: The invention consists of a barometric pressure sensor, coupled to a processor for recording changes in the pressure over time, this is coupled to a GPS device providing an accurate measurement of the altitude which allows for the barometric pressure measurements to be normalized, typically to mean sea level. Once the measurements have been normalized the effects of the vertical motion of the sensor are effectively removed and the resulting trend shows the absolute atmospheric pressure which can then be used for weather prediction.

Abstract: A GNSS platform architecture with advanced tracking and search engines. The tracking and search functions are separated into 2 independent engines each highly optimized for their targeted functions.

Abstract: A code generator, for providing a PRN sequence in a GNSS receiver, has the capability to store an internal status at any given point of the generated sequence. The stored status can be reloaded in the generator, upon an external command, or after a given number of generation cycles, thus slewing the phase of the generated PRN sequence to the value corresponding to the stored status. A parallel-correlation GNSS receiver includes one or more slewable code generators, for successively generating local replicas of GNSS PRN sequences, having different code phases, corresponding to a plurality of candidate signals of different code and Doppler shifts. Each time the code generator must switch from one candidate to a second, it is preemptively controlled or programmed, while generating the code for the first candidate, to store the internal status at the phase point almost aligned with the start of the PRN sequence for the second candidate.

Abstract: A signal processor for GPS or other GNSS radiolocalization systems, includes a RAM pre-correlation buffer which is filled in sync with the code NCO, thus all sample alignment in the buffer is fixed The device further includes an amplitude compressor to limit the size of the buffer memory and is optimized to provide data to the following DFT unit in small bursts that can be processed in real time without the need for intermediate buffers. Thanks to these features the processor limits the amount of fast intermediate memories, is simpler and has lowerpower consumption.