Patents by Inventor Philip Joseph Lauriello

Philip Joseph Lauriello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11172572
    Abstract: A multilayer electronics assembly and associated method of manufacture are provided. The multilayer electronics assembly includes a plurality of stacked substrate layers. Each of the substrate layers is fusion bonded to at least an adjacent one of the plurality of substrate layers. A first discrete electrical circuit component is bonded to a first layer of the plurality of layers. A bonding material is interposed between the discrete electrical circuit component and the first layer. The bonding material has a reflow temperature at which the bonding material becomes flowable that is higher than a fusion bonding temperature of the substrate layers.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: November 9, 2021
    Assignee: Crane Electronics, Inc.
    Inventors: Ernest Clyde Parker, Philip Joseph Lauriello
  • Publication number: 20180146547
    Abstract: A multilayer electronics assembly and associated method of manufacture are provided. The multilayer electronics assembly includes a plurality of stacked substrate layers. Each of the substrate layers is fusion bonded to at least an adjacent one of the plurality of substrate layers. A first discrete electrical circuit component is bonded to a first layer of the plurality of layers. A bonding material is interposed between the discrete electrical circuit component and the first layer. The bonding material has a reflow temperature at which the bonding material becomes flowable that is higher than a fusion bonding temperature of the substrate layers.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 24, 2018
    Inventors: Ernest Clyde PARKER, Philip Joseph LAURIELLO
  • Patent number: 9888568
    Abstract: A multilayer electronics assembly and associated method of manufacture are provided. The multilayer electronics assembly includes a plurality of stacked substrate layers. Each of the substrate layers is fusion bonded to at least an adjacent one of the plurality of substrate layers. A first discrete electrical circuit component is bonded to a first layer of the plurality of layers. A bonding material is interposed between the discrete electrical circuit component and the first layer. The bonding material has a reflow temperature at which the bonding material becomes flowable that is higher than a fusion bonding temperature of the substrate layers.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: February 6, 2018
    Assignee: CRANE ELECTRONICS, INC.
    Inventors: Ernest Clyde Parker, Philip Joseph Lauriello
  • Patent number: 6124957
    Abstract: The invention is directed to an optical node, e.g., a so-called add/drop site, that receives an optical carrier signal formed from a plurality of component optical signals of respective wavelengths and a plurality of different identification signals which identify respective ones of the wavelengths. As is typically the case, the node includes a demultiplexer that demultiplexes the optical carrier signal and outputs the demultiplexed component optical signals to respective optical paths. Disadvantageously, each of the demultiplexed optical component signals includes all of the identification signals as a result of such demultiplexing. However, we dispose an optical translator unit in at least one of the optical paths to remove all of the identification signals from the one component optical signals and also reset the power level of that signal.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: September 26, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Vibha Prakash Goel, Steven Russell Johnson, Joseph P. Kunz, Philip Joseph Lauriello, Stan Lumish, Frank J. Peragine