Patents by Inventor Philip Kruzinski
Philip Kruzinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9621290Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.Type: GrantFiled: March 29, 2016Date of Patent: April 11, 2017Assignee: Juniper Networks, Inc.Inventors: Charles F. Barry, Meenakshi S. Subramanian, Feng Frank Pan, Tian (Alan) Shen, Philip Kruzinski, Guochun (George) Zhao, DeviPrasad Natesan, David R. Jorgensen
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Publication number: 20160211937Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.Type: ApplicationFiled: March 29, 2016Publication date: July 21, 2016Applicant: Juniper Networks, Inc.Inventors: Charles F. Barry, Meenakshi S. Subramanian, Feng Frank Pan, Tian (Alan) Shen, Philip Kruzinski, Guochun (George) Zhao, DeviPrasad Natesan, David R. Jorgensen
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Patent number: 9319164Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.Type: GrantFiled: July 17, 2013Date of Patent: April 19, 2016Assignee: Juniper Networks, Inc.Inventors: Charles F. Barry, Meenakshi S. Subramanian, Feng Frank Pan, Tian (Alan) Shen, Philip Kruzinski, Guochun (George) Zhao, DeviPrasad Natesan, David R. Jorgensen
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Patent number: 8954609Abstract: In one example, network device includes a control unit having one or more hardware-based microprocessors and an interface. The interface can receive a first time synchronization message from a master device that comprises a first TTL value. The first TTL value can be indicative of a number of hops traversed by the first time synchronization message. The interface can subsequently receive a second time synchronization message from the master device that comprises a second TTL value that is is indicative of a number of hops traversed by the second time synchronization message. The network device can also include a timing module that determines a time adjustment based at least in part on the determination that the first and second TTL values are different, and applies the time adjustment to update the time of the network device.Type: GrantFiled: April 25, 2012Date of Patent: February 10, 2015Assignee: Juniper Networks, Inc.Inventors: Keith E. Holleman, Murthy Garikiparthi, Meenakshi Sundaram Subramanian, DeviPrasad Natesan, Philip Kruzinski
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Publication number: 20130301660Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.Type: ApplicationFiled: July 17, 2013Publication date: November 14, 2013Applicant: Juniper Networks, Inc.Inventors: Charles F. Barry, Meenakshi S. Subramanian, Feng Frank Pan, Tian (Alan) Shen, Philip Kruzinski, Guochun (George) Zhao, DeviPrasad Natesan, David R. Jorgensen
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Patent number: 8494011Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.Type: GrantFiled: September 13, 2012Date of Patent: July 23, 2013Assignee: Juniper Networks, Inc.Inventors: Charles F. Barry, Meenakshi S. Subramanian, Feng Frank Pan, Tian Alan Shen, Philip Kruzinski, Guochun George Zhao, DeviPrasad Natesan, David R. Jorgensen
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Publication number: 20130010815Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.Type: ApplicationFiled: September 13, 2012Publication date: January 10, 2013Applicant: Juniper Networks, Inc.Inventors: Charles F. Barry, Meenakshi S. Subramanian, Feng Frank Pan, Tian (Alan) Shen, Philip Kruzinski, Guochun (George) Zhao, DeviPrasad Natesan, David R. Jorgensen
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Patent number: 8270438Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.Type: GrantFiled: August 30, 2011Date of Patent: September 18, 2012Assignee: Juniper Networks, Inc.Inventors: Charles F. Barry, Meenakshi S. Subramanian, Feng Frank Pan, Tian Alan Shen, Philip Kruzinski, Guochun George Zhao, DeviPrasad Natesan, David R. Jorgensen
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Publication number: 20110310766Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.Type: ApplicationFiled: August 30, 2011Publication date: December 22, 2011Applicant: JUNIPER NETWORKS, INC.Inventors: Charles F. Barry, Meenakshi S. Subramanian, Feng Frank Pan, Tian (Alan) Shen, Philip Kruzinski, Guochun George Zhao, DeviPrasad Natesan, David R. Jorgensen
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Patent number: 8031747Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.Type: GrantFiled: April 29, 2009Date of Patent: October 4, 2011Assignee: Juniper Networks, Inc.Inventors: Charles F. Barry, Meenakshi S. Subramanian, Feng Frank Pan, Tian (Alan) Shen, Philip Kruzinski, Guochun (George) Zhao, DeviPrasad Natesan, David R. Jorgensen
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Publication number: 20100278055Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.Type: ApplicationFiled: April 29, 2009Publication date: November 4, 2010Inventors: Charles F. Barry, Meenakshi S. Subramanian, Feng Frank Pan, Tian (Alan) Shen, Philip Kruzinski, Guochun (George) Zhao, DeviPrasad Natesan, David R. Jorgensen
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Patent number: 5408469Abstract: A data communications network providing for a multiport router and providing for use of an asynchronous transfer mode (ATM) switch or the like as a routing backplane or packet switching engine. A router front end formats ATM cells including providing routing information in the cell header. The routing information may comprise, for example, a destination port identifier in the VPI field of the cell header. The ATM switch then switches the cell from an input port, coupled with the router front end to an output port based on the routing information. The ATM switch may also translate the routing information to provide source identification information to the destination. In a described embodiment, the multiport router is used as a backplane bus in a network concentrator.Type: GrantFiled: July 22, 1993Date of Patent: April 18, 1995Assignee: SynOptics Communications, Inc.Inventors: Ayal Opher, Gaurav Garg, Philip Kruzinski, Som Sikdar