Patents by Inventor Philip L. Craine

Philip L. Craine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for tracking casino promotional funds and apparatus for use therewith
    Patent number: 5321241
    Abstract: A system for tracking casino promotional funds given to a casino patron, comprising a plurality of gaming machines A bank controller is provided for the plurality of gaming machines. A server is connected to the bank controller. A plurality of memory devices are provided. Each memory device has a memory which has encoded therein an identification of a serial number which is assigned to a casino patron receiving the memory device. The system provides an account balance for the casino patron which is associated with the memory device supplied to the casino patron. An interface device is provided on each gaming machine and is adapted to interface with the memory device to permit operation of the gaming machine and to permit debiting of the account balance of the casino patron as the gaming machine is operated by the casino patron utilizing the assigned memory device.
    Type: Grant
    Filed: March 19, 1993
    Date of Patent: June 14, 1994
    Assignee: Calculus Microsystems Corporation
    Inventor: Philip L. Craine
  • Scheme for eliminating page boundary limitation on initial access of a serial contiguous access memory
    Patent number: 5285421
    Abstract: In accordance with the present invention, a memory system capable of indefinite sequential access to a contiguous address space without stutter is provided. The memory system has a memory array divided into left and right halves, column and row decoders, memory output register banks A and B, and control logic. Upon initial access, the control logic determines whether, in the initial access data to be loaded in register banks A and B cross a row address boundary. If a row address boundary is crossed, data loaded into register bank A corresponds to data in one row in the right half of the memory array, and data in register bank B corresponds to data in the left half of the memory array in the next higher row. Thereafter, register banks A and B are interleaved for loading and output of memory data.
    Type: Grant
    Filed: March 31, 1992
    Date of Patent: February 8, 1994
    Assignee: Advanced Micro Devices
    Inventors: Elvan S. Young, Philip L. Craine
  • Architecture for high speed contiguous sequential access memories
    Patent number: 5280594
    Abstract: In accordance with the present invention, by interleaving two banks of memory output registers, a memory system is provided which allows an indefinite number of sequential accesses to contiguous locations of the memory system, requiring only a reduced access time per output datum after the first initial access, regardless of whether row address boundaries are crossed.
    Type: Grant
    Filed: July 25, 1990
    Date of Patent: January 18, 1994
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Elvan S. Young, Philip L. Craine