Patents by Inventor Philip L. Flaitz
Philip L. Flaitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7951708Abstract: A method of forming a diffusion barrier for use in semiconductor device manufacturing includes depositing, by a physical vapor deposition (PVD) process, an iridium doped, tantalum based barrier layer over a patterned interlevel dielectric (ILD) layer, wherein the barrier layer is deposited with an iridium concentration of at least 60 atomic % such that the barrier layer has a resulting amorphous structure.Type: GrantFiled: June 3, 2009Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Patrick W. DeHaven, Daniel C. Edelstein, Philip L. Flaitz, Takeshi Nogami, Stephen M. Rossnagel, Chih-Chao Yang
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Publication number: 20100311236Abstract: A method of forming a diffusion barrier for use in semiconductor device manufacturing includes depositing, by a physical vapor deposition (PVD) process, an iridium doped, tantalum based barrier layer over a patterned interlevel dielectric (ILD) layer, wherein the barrier layer is deposited with an iridium concentration of at least 60% by atomic weight such that the barrier layer has a resulting amorphous structure.Type: ApplicationFiled: June 3, 2009Publication date: December 9, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Patrick W. DeHaven, Daniel C. Edelstein, Philip L. Flaitz, Takeshi Nogami, Stephen M. Rossnagel, Chih-Chao Yang
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Patent number: 7820559Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: GrantFiled: June 23, 2008Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Darren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang
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Publication number: 20080254643Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: ApplicationFiled: June 23, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Darren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang
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Patent number: 7402532Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: GrantFiled: August 4, 2006Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Derren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang
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Patent number: 7102232Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: GrantFiled: April 19, 2004Date of Patent: September 5, 2006Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Derren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang
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Patent number: 6960514Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.Type: GrantFiled: March 18, 2004Date of Patent: November 1, 2005Assignee: International Business Machines CorporationInventors: Jochen Beintner, Rama Divakaruni, Johnathan Faltermeier, Philip L. Flaitz, Oleg Gluschenkov, Carol J. Heenan, Rajarao Jammy, Byeong Kim, Mihel Seitz, Akira Sudo, Yoichi Takegawa
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Publication number: 20040173858Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.Type: ApplicationFiled: March 18, 2004Publication date: September 9, 2004Inventors: Jochen Beintner, Rama Divakaruni, Johnathan Faltermeier, Philip L. Flaitz, Oleg Gluschenkov, Carol J. Heenan, Rajarao Jammy, Byeong Kim, Mihel Seitz, Akira Sudo, Yoichi Takegawa
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Patent number: 6746933Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.Type: GrantFiled: October 26, 2001Date of Patent: June 8, 2004Assignee: International Business Machines CorporationInventors: Jochen Beintner, Rama Divakaruni, Johnathan Faltermeier, Philip L. Flaitz, Oleg Gluschenkov, Carol J. Heenan, Rajarao Jammy, Byeong Kim, Mihel Seitz, Akira Sudo, Yoichi Takegawa
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Patent number: 6740568Abstract: In a method of forming a contact, a liner reactive ion etch is affected on a substrate to remove silicon nitride and silicon oxide. An oxygen plasma ex-situ clean, a Huang AB clean, and a dilute hydrofluric acid (DHF) clean are affected. Amorphous silicon is deposited and an anneal is performed to regrow and recrystallize amorphous silicon.Type: GrantFiled: July 29, 2002Date of Patent: May 25, 2004Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Yun Yu Wang, Johnathan Faltermeier, Colleen M. Snavely, Michael Maldei, Michael M. Iwatake, David M. Dobuzinsky, Ravikumar Ramachandran, Viraj Y. Sardesai, Philip L. Flaitz, Lisa Y. Ninomiya
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Patent number: 6707086Abstract: In accordance with the present invention, a method for forming a crystalline silicon nitride layer, includes the steps of providing a crystalline silicon substrate with an exposed surface, precleaning the exposed surface by employing a hydrogen prebake and exposing the exposed surface to nitrogen to form a crystalline silicon nitride layer. Also, a trench capacitor, in accordance with the present invention, includes a crystalline silicon substrate including deep trenches having surface substantially free of native oxide. A dielectric stack, including a crystalline silicon nitride layer, is formed on the sidewalls of the trenches. The dielectric stack forms a node dielectric between electrodes of the trench capacitor.Type: GrantFiled: June 15, 2000Date of Patent: March 16, 2004Assignees: Infineon Technologies AG, International Business Machines Corp.Inventors: Rajarao Jammy, Philip L. Flaitz, Philip E. Batson, Hua Shen, Yun Yu Wang
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Publication number: 20040018680Abstract: In a method of preparing a DRAM wherein doped poly-Si is used as a CB contact as well as a source of doping in the contact region, and whereType: ApplicationFiled: July 29, 2002Publication date: January 29, 2004Inventors: Yun Yu Wang, Johnathan Faltermeier, Colleen M. Snavely, Michael Maldei, Michael M. Iwatake, David M. Dobuzinsky, Ravikumar Ramachandran, Viraj Y. Sardesai, Philip L. Flaitz, Lisa Y. Ninomiya
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Publication number: 20020182893Abstract: Disclosed is a method to convert a stable silicon nitride film into a stable silicon oxide film with a low content of residual nitrogen in the resulting silicon oxide film. This is an unexpected and unique property of the in situ steam generation process since both silicon nitride and silicon oxide materials are chemically very stable compounds. Application of the claimed method to the art of microelectronic device fabrication, such as fabrication of on-chip dielectric capacitors and metal insulator semiconductor field effect transistors, is also disclosed.Type: ApplicationFiled: June 5, 2001Publication date: December 5, 2002Applicant: International Business Machines CorporationInventors: Arne W. Ballantine, Johnathan E. Faltermeier, Philip L. Flaitz, Jeffrey D. Gilbert, Oleg Gluschenkov, Carol J. Heenan, Rajarao Jammy, Ryota Katsumada
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Publication number: 20020137362Abstract: In accordance with the present invention, a method for forming a crystalline silicon nitride layer, includes the steps of providing a crystalline silicon substrate with an exposed surface, precleaning the exposed surface by employing a hydrogen prebake and exposing the exposed surface to nitrogen to form a crystalline silicon nitride layer. Also, a trench capacitor, in accordance with the present invention, includes a crystalline silicon substrate including deep trenches having surface substantially free of native oxide. A dielectric stack, including a crystalline silicon nitride layer, is formed on the sidewalls of the trenches. The dielectric stack forms a node dielectric between electrodes of the trench capacitor.Type: ApplicationFiled: July 29, 1999Publication date: September 26, 2002Inventors: RAJARAO JAMMY, PHILIP L. FLAITZ, PHILIP E. BATSON, HUA SHEN, YUN YU WANG
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Patent number: 6333531Abstract: A process for forming a small grain structure in a material within a semiconductor device near the interface of an adjacent dissimilar material, to result in a highly diffusive grain structure. The highly diffusive grain structure formed within one material enhances diffusion of a dopant impurity, and provides for improved dopant control in an adjacent dissimilar material.Type: GrantFiled: January 29, 1999Date of Patent: December 25, 2001Assignee: International Business Machines CorporationInventors: Yun-Yu Wang, Johnathan E. Faltermeier, Philip L. Flaitz, Jeffery L. Hurd, Rajarao Jammy, Radhika Srinivasan, Francis G. Trudeau, Dinah S. Weiss
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Patent number: 5167913Abstract: A method of forming an adherent layer of metallurgy on a ceramic substrate which includes the steps of obtaining a ceramic material containing a polymeric binder and copper metallurgy patterns within the ceramic body. In one embodiment of the invention, the ceramic body also contains MgO.Thereafter, a surface layer of metallurgy is formed on the surface of the ceramic body. In one embodiment, the surface layer is nickel and in another embodiment, the surface layer is copper or gold.Then, the ceramic body undergoes a sintering cycle which includes the steps of pyrolysis, binder burnoff and, lastly, densification and, in some cases, crystallization. During densification and crystallization, there is a predetermined steam atmosphere which meets the following requirements: a partial pressure of oxygen less than that necessary to satisfy the equilibrium equation 4Cu+O.sub.2 =2Cu.sub.2 O; and a partial pressure of oxygen less than or equal to that necessary to satisfy the equilibrium equation 2Ni+O.sub.Type: GrantFiled: December 23, 1991Date of Patent: December 1, 1992Assignee: International Business Machines CorporationInventors: John Acocella, Philip L. Flaitz, Raj N. Master, Chandrasekhar Narayan, Sarah H. Knickerbocker, Paul H. Palmateer, Sampath Purushothaman, Srinivasa S. N. Reddy
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Patent number: 5130067Abstract: A method for co-sintering ceramic/metal multi-layered ceramic substrates wherein X-Y shrinkage is controlled and X-Y distortion and Z-direction chamber are substantially eliminated. Binder-burnoff is substantially not aggravated during this process as well. The process is accomplished by applying selective forces to the surfaces of the ceramic substrates to control lateral movement while allowing Z direction shrinkage movement. Frictional force means, pneumatic forced means and weights are among the means used to supply forces. Cerium oxide is used in certain embodiments to enhance binder-burnoff.Type: GrantFiled: May 2, 1986Date of Patent: July 14, 1992Assignee: International Business Machines CorporationInventors: Philip L. Flaitz, Arlyne M. Flanagan, Joseph M. Harvilchuck, Lester W. Herron, John U. Knickerbocker, Robert W. Nufer, Charles H. Perry, Srinivasa N. Reddy, Steven P. Young
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Patent number: 4764341Abstract: The bonding of nickel, cobalt, copper or any number of metals to oxide ceramics is achieved whereby the substrate and associated metallurgy are co-sintered. The invention teaches the use of an intermediary oxide such as Al2O3, Cr2O3, TiO2 or ZrO2 which will adhere to the substrate and in the presence of firing ambients form a complex ternary oxide with the overlying metal thereby creating the desired bond. The eutectic can be created during the firing cycle without the undesired consequence of oxidizing the metal. The so-called intermediary oxides can be oxidized in situ, deposited as oxides, or introduced into either the ceramic composition or the metal paste.Type: GrantFiled: April 27, 1987Date of Patent: August 16, 1988Assignee: International Business Machines CorporationInventors: Philip L. Flaitz, Raj N. Master, Paul H. Palmateer, Srinivasa S. N. Reddy
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Patent number: 4755631Abstract: Apparatus is described for providing an electrical connection to a metallic pad situated on a brittle dielectric substrate, such as a multi-layered ceramic (MLC) substrate, that reduces tensile stress occurring between the pad and the substrate.Type: GrantFiled: March 19, 1987Date of Patent: July 5, 1988Assignee: International Business Machines CorporationInventors: Robert W. Churchwell, Philip L. Flaitz, James N. Humenik
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Patent number: 4672739Abstract: A method for use in brazing an interconnect pin to a portion of metallization pattern (e.g. a pad) existing on a brittle dielectric substrate, such as a multi-layered ceramic (MLC) substrate, is disclosed. A dielectric layer is formed with appropriate annular openings. Each opening provides a closed containment wall, which extends around and above the pad, to hold the brazing alloy. Each circular containment wall is concentrically aligned with its associated pad and exposes an area, of each pad, having a smaller diameter than that of the entire pad. The containment walls serve to prevent the brazing alloy from coming into contact with any edge of the pads.Type: GrantFiled: April 11, 1985Date of Patent: June 16, 1987Assignee: International Business Machines CorporationInventors: Robert W. Churchwell, Philip L. Flaitz, James N. Humenik