Abstract: Various embodiments provide apparatuses, systems, and methods for automatic phase scaling (APS) of dynamic voltage ID (DVID) in a voltage regulator. Other embodiments may be described and claimed.

Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Abstract: Described are mechanisms and methods for reducing CPU power upon interruption of a supplied power. In some embodiments, an apparatus may comprise an input to receive an indicator that a supply voltage to a computer system has been interrupted. The apparatus may comprise an output to provide an indicator to reduce a processor power consumption level. The apparatus may also comprise a circuitry to establish the indicator to reduce the processor power level based upon the indicator that the supply voltage to the computer system has been interrupted.

Abstract: Power monitoring circuitry is provided to monitor an input system power profile of processing tasks executing on a processing platform. An input is provided to receive from the processing platform, a processing system signal indicating a power being consumed by the processing platform. A counter is provided to store a count value corresponding to an accumulated number or amount of times that a warning threshold condition associated with a warning threshold value is satisfied by the received processing system signal in a count-accumulation time interval. The count value is supplied to a power control circuit of the processing platform via a bus in response to a read request from the power control circuit, the power control circuit being responsive to the count value to control a performance level of the processing platform.

Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Abstract: Described are mechanisms and methods for reducing CPU power upon interruption of a supplied power. In some embodiments, an apparatus may comprise an input to receive an indicator that a supply voltage to a computer system has been interrupted. The apparatus may comprise an output to provide an indicator to reduce a processor power consumption level. The apparatus may also comprise a circuitry to establish the indicator to reduce the processor power level based upon the indicator that the supply voltage to the computer system has been interrupted.

Abstract: Power monitoring circuitry is provided to monitor an input system power profile of processing tasks executing on a processing platform. An input is provided to receive from the processing platform, a processing system signal indicating a power being consumed by the processing platform. A counter is provided to store a count value corresponding to an accumulated number or amount of times that a warning threshold condition associated with a warning threshold value is satisfied by the received processing system signal in a count-accumulation time interval. The count value is supplied to a power control circuit of the processing platform via a bus in response to a read request from the power control circuit, the power control circuit being responsive to the count value to control a performance level of the processing platform.

Abstract: In some embodiments, a method, apparatus and system for enabling and disabling voltage regulator controllers are generally presented. In this regard, a sequencer agent is introduced to selectively enable or disable the outputs of voltage regulator controllers in an electronic appliance based at least in part on settings stored in non-volatile memory. Other embodiments are discussed and claimed.