Patents by Inventor Philip M. Henault
Philip M. Henault has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250107006Abstract: A printed circuit board comprises a support structure, a conductive layer operably coupled to the support structure, a mask structure formed on the conductive layer, and a cover layer. The conductive layer comprises first and second portions of conductive material separated by a gap that defines a spacing between the first and second portions that does not contain conductive material. The mask structure defines first and second regions on the conductive layer. The first region is enclosed by a first boundary defined by the mask structure and includes the gap. The second region lies outside of the first boundary. The cover layer is sized to fit within the first region and comprises a laminatible insulating material that flows within the first region during lamination. During lamination, the first boundary prevents the laminatible insulating material from flowing into the second region, and the laminatible insulating material flows to fill the gap.Type: ApplicationFiled: September 21, 2023Publication date: March 27, 2025Applicant: Raytheon CompanyInventors: Angelo M. Puzella, Philip M. Henault, Alexander B. Brailovsky
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Patent number: 11558957Abstract: An electronic assembly including a thermal capacitor. An electronic substrate of the electronic assembly includes one or more insulating layers and one or more conductor layers provided along the one or more insulating layers. The one or more conductor layers including a conductive material. A shape memory thermal capacitor is received in the electronic substrate. The shape memory thermal capacitor includes a shape memory core including a shape memory material.Type: GrantFiled: June 12, 2020Date of Patent: January 17, 2023Assignees: Raytheon Company, THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE ARMYInventors: David H. Altman, Christopher H. Peters, Gregory P. Schaefer, Philip M. Henault, Darin J. Sharar
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Publication number: 20210392737Abstract: An electronic assembly including a thermal capacitor. An electronic substrate of the electronic assembly includes one or more insulating layers and one or more conductor layers provided along the one or more insulating layers. The one or more conductor layers including a conductive material. A shape memory thermal capacitor is received in the electronic substrate. The shape memory thermal capacitor includes a shape memory core including a shape memory material.Type: ApplicationFiled: June 12, 2020Publication date: December 16, 2021Inventors: David H. Altman, Christopher H. Peters, Gregory P. Schaefer, Philip M. Henault, Darin J. Sharar
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Patent number: 10276282Abstract: A coaxial transmission line structure having a center conductor section having an input contact and an output contact the output contact being larger than the input contact, the center conductor having a plurality of different geometrically shaped, electrically conductive layers having sizes progressively increasing from the input contact to the larger output contact to conductor transition from the input contact to the larger output contact, the electrically conductive layers being electrically interconnected by staggered microvias passing through dielectric layers to the center, and (B) an outer conductor section disposed about, coaxial with, and electrically isolated from, the center conductor by the dielectric layers.Type: GrantFiled: July 28, 2017Date of Patent: April 30, 2019Assignee: Raytheon CompanyInventors: Angelo M. Puzella, Lance A. Auer, Norman Armendariz, Donald A. Bozza, John B. Francis, Philip M. Henault, Randal W. Oberle, Susan C. Trulli, Dimitry Zarkh
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Publication number: 20190035517Abstract: A coaxial transmission line structure having a center conductor section having an input contact and an output contact the output contact being larger than the input contact, the center conductor having a plurality of different geometrically shaped, electrically conductive layers having sizes progressively increasing from the input contact to the larger output contact to conductor transition from the input contact to the larger output contact, the electrically conductive layers being electrically interconnected by staggered microvias passing through dielectric layers to the center, and (B) an outer conductor section disposed about, coaxial with, and electrically isolated from, the center conductor by the dielectric layers.Type: ApplicationFiled: July 28, 2017Publication date: January 31, 2019Applicant: Raytheon CompanyInventors: Angelo M. Puzella, Lance A. Auer, Norman Armendariz, Donald A. Bozza, John B. Francis, Philip M. Henault, Randal W. Oberle, Susan C. Trulli, Dimitry Zarkh
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Publication number: 20180183146Abstract: A via-less beamformer provided from a plurality of circuits elements having circuit layouts selected to mitigate unwanted reactive coupling there between. At least one of the plurality of circuit elements is provided having a circuit layout selected based upon reactive field theory. In one embodiment, a circuit layout may be selected by: determining which circuit features of the circuit elements produce reactive fields in response to a signal provided thereto, separating the total field into a modal set and determining the modal weighting coefficients based on geometrical and/or design features of the of the circuit elements. In one embodiment the via-less beamformer comprises one or more via-less combiner/divider circuits. In one embodiment the via-less beamformer comprises one or more branch hybrid coupler circuits. In one embodiment the via-less beamformer comprises one or more via-less combiner/divider circuits and one or more branch hybrid coupler circuits.Type: ApplicationFiled: December 27, 2016Publication date: June 28, 2018Applicant: Raytheon CompanyInventors: Thomas V. Sikina, John P. Haven, Philip M. Henault, Alkim Akyurtlu
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Patent number: 9584080Abstract: A power amplifier structure having: a power divider for dividing power in a signal fed to an input port between a pair of output ports. Each one of a pair of amplifiers has: an input coupled to a corresponding one of the pair of power divider output ports; and an output. A power combiner is provided. Signals at the power divider output ports are fed to the inputs of the pair of amplifiers in a forward direction and then pass through the amplifiers in the forward direction towards the outputs of the pair of amplifiers. Connectors direct the signals at the amplifier outputs to the power combiners, the signal then passing through the power combiner to an output port in a direction opposite to the forward direction.Type: GrantFiled: February 23, 2015Date of Patent: February 28, 2017Assignee: Raytheon CompanyInventors: Christopher M. Laighton, James A. Robbins, Jonathan B. Langille, Philip M. Henault
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Publication number: 20160248392Abstract: A power amplifier structure having: a power divider for dividing power in a signal fed to an input port between a pair of output ports. Each one of a pair of amplifiers has: an input coupled to a corresponding one of the pair of power divider output ports; and an output. A power combiner is provided. Signals at the power divider output ports are fed to the inputs of the pair of amplifiers in a forward direction and then pass through the amplifiers in the forward direction towards the outputs of the pair of amplifiers. Connectors direct the signals at the amplifier outputs to the power combiners, the signal then passing through the power combiner to an output port in a direction opposite to the forward direction.Type: ApplicationFiled: February 23, 2015Publication date: August 25, 2016Applicant: Raytheon CompanyInventors: Christopher M. Laighton, James A. Robbins, Jonathan B. Langille, Philip M. Henault