Abstract: The disclosure teaches various logic circuits operating with Dynamic Differential Logic (DDL). In a particular embodiment MOS transistors of n-channel type are used with circuits arranged to avoid any dc path from clock input to ground. The input capacitance of the active devices is used for temporary storage thereby reducing circuit complexities. Coupling between stages is provided by clock driven transistors connected so that the transistor at the higher voltage side cuts off early in the period of clock pulse decay, thereby isolating adjacent stages without unnecessary delay. The use of such circuits in array processors is described.

Abstract: The apparatus generates a train of pulse signals in real time which are fed to a Plan Position Indicator radar display video bright-up circuit. A line is formed on the display at a bearing .theta..sub.R , the direction of a VHF/DF fix, and passes through a point having the coordinates R.sub.o, .angle..theta..sub.o .degree., the position of the VHF/DF receiver, with respect to the center of the plan position indicator rotating radial scan. The radial scan operates at a radar trigger pulse repetition frequency F and rotates at a frequency f to subtend an angle .DELTA..theta.=360.degree..times.f/F per scan. The apparatus includes an up-counter for storing a count of R.sub.o sin (.theta..sub.R -.theta..sub.o), and a down-counter coupled to the up-counter and enabled at the pulse repetition frequency F to receive the count from the up-counter. The down-counter is adapted to provide an output pulse signal to the video bright-up circuit when its count reaches 0.