Abstract: A data processor, such as a graphics processor, is disclosed. The data processor includes a set of one or more counters, and a control circuit that maintains a cache-like pool of corresponding entries. In response to a request for a counter, the control circuit may allocate an entry of the cache-like pool to thereby allocate a counter of the set.

Abstract: There is a communications network node comprising a transmitter or a receiver configured to communicate with a plurality of other nodes via an interconnection medium interconnecting the node and the other nodes. The node is frequency synchronized with regard to signal transmission or reception, via a frequency synchronization mechanism, with at least one of the other nodes. The node has at least one store holding phase data relating to an amount of phase asynchrony and path characteristics between the node and at least one of the other nodes. A phase controller uses the stored data to adjust phase used by the node such that the recovery of data when communicating with at least one other node is facilitated.