Abstract: An apparatus is provided for monitoring heart rate. The apparatus comprises various components to effectively reduce photodiode capacitance. The apparatus includes: an amplifier; a first current source; a first pair of resistors coupled to the first current source and the amplifier; a pair of devices coupled to the first pair of resistors; a photo-diode coupled to the pair of devices; a second pair of resistors coupled to the pair of devices and the photo-diode; and a second current source coupled to the second pair of resistors.

Abstract: A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad.

Abstract: A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad.

Abstract: A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad.

Abstract: A comparator with an input stage that selectively powers up an output stage provides an electronic device with a comparator that operates at low power. In an embodiment, an input stage produces a near decision and a true decision, where the near decision is provided to power up an output stage for the comparator to provide an output representative of the true decision.

Abstract: A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad.

Abstract: A bias readout circuit is disclosed for use in reading out a pixel of an imager system. The bias readout circuit includes a circuit portion which mirrors an output and bias transistor of a pixel to amplify an output signal produced by a pixel and increase the dynamic range of the pixel output.

Abstract: A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: A CMOS bandgap reference (BGR) voltage generator circuit has a passive resistor T-network of low resistance connected between the inverting and non-inverting inputs of the op-amp in the circuit. The op-amp's output is connected to the gates of three PMOS transistors and the drains of two of the transistors are connected in a looped manner to the input terminals of the op-amp. The T-network is placed between these drains that connect to the op-amp. Becuse of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: A signal balancing circuit for capacitively coupled signaling between transmitting and receiving devices over a plurality of capacitively coupled signal lines on which data signals are transmitted from the transmitting device to the receiving device. The signal balancing circuit includes an encode circuit for forcing a signal transition of a data signal for a data interval in response to the data signal maintaining the same logic state throughout a respective time interval. A balancing signal is generated having a logic level and a timing relative to the time intervals of the respective data signals indicative of inversion of a particular data signal. A decode circuit coupled to the encode circuit to receive the balancing signal forces a transition of the transitioned signal at the appropriate time in accordance with the balance signal to recover the original logic level of the data signal.