Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

Abstract: A microelectronic package including a dielectric element with at least one conductive ground pad. The package may also include a microelectronic element with at least one ground contact exposed at a rear surface of the element. The ground pad and the ground contact are electrically connected to each other by an electrically conducting material.

Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

Abstract: A connection component for a semiconductor chip includes a substrate having a gap over which extends a plurality of parallel spaced apart leads. The ends of the leads are adhered to the substrate either by being bonded to contacts or being embedded in the substrate. The connection component can be formed, in one embodiment, by stitch bonding wire leads across the gap. In another embodiment, a prefabricated lead assembly supporting spaced apart parallel leads is juxtaposed and transferred to the substrate. The connection component is juxtaposed overlying a semiconductor chip whereby leads extending over the gap may have one end detached and bonded to an underlying chip contact.

Abstract: Various embodiments of packaged chips and ways of fabricating them are disclosed herein. One such packaged chip disclosed herein includes a chip having a front face, a rear face opposite the front face, and a device at one of the front and rear faces, the device being operable as a transducer of at least one of acoustic energy and electromagnetic energy, and the chip including a plurality of bond pads exposed at one of the front and rear faces. The packaged chip includes a package element having a dielectric element and a metal layer disposed on the dielectric element, the package element having an inner surface facing the chip and an outer surface facing away from the chip. The metal layer includes a plurality of contacts exposed at at least one of the inner and outer surfaces, the contacts conductively connected to the bond pads.

Abstract: Various embodiments of packaged chips and ways of fabricating them are disclosed herein. One such packaged chip disclosed herein includes a chip having a front face, a rear face opposite the front face, and a device at one of the front and rear faces, the device being operable as a transducer of at least one of acoustic energy and electromagnetic energy, and the chip including a plurality of bond pads exposed at one of the front and rear faces. The packaged chip includes a package element having a dielectric element and a metal layer disposed on the dielectric element, the package element having an inner surface facing the chip and an outer surface facing away from the chip. The metal layer includes a plurality of contacts exposed at at least one of the inner and outer surfaces, the contacts conductively connected to the bond pads.

Abstract: A microelectronic fold package is formed from an in-process unit including an internal unit such as a chip and a tape defining a bottom run extending beneath the internal unit, a top run extending above the internal unit and a fold connecting said top and bottom runs. The in-process unit is engaged between a pair of elements having flat surfaces so that these elements form the top and bottom runs to a substantially flat condition at least in regions between the internal unit and the fold and so that the engagement elements form the fold to a height equal to the height of the internal unit.

Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

Abstract: A method of manufacturing a plurality of semiconductor chips packages and the resulting chip package assemblies. The method includes providing a circuitized substrate having terminals and leads. A spacer layer is deposited or attached to the substrate and each chip is then attached to the spacer layer. Typically, the spacer layer is comprised of a compliant or resilient material. The terminals and leads are interconnected using leads, at least some of which are fan-out leads. A ring-like pattern of a curable composition is disposed around each chip and cured to form a support structure. The assembly is encapsulated by dispensing a composition which is curable to an encapsulant into the gaps between the support structures and the chips. The encapsulant material is then cured thereby defining a composite of chip assemblies which may be singulated into individual chip packages.