Abstract: Disclosed and claimed herein is an improved leg brace having a thigh frame, a shank frame, a knee assembly rotatably coupling the thigh frame to the shank frame, and a shoe component attached to the shank frame; the knee assembly having a spring, clutch, means for engaging the clutch; and programmable means for engaging the clutch at a selected angle between the thigh frame and shank frame.

Abstract: Disclosed and claimed herein are spiral torsion springs, non-linear torsion springs, and non-linear torsion spring assemblies. These devices are useful in damping applications, orthotic joint applications and servo control applications.

Abstract: Disclosed and claimed herein is an improved leg brace having a thigh frame, a shank frame, a knee assembly rotatably coupling the thigh frame to the shank frame, and a shoe component attached to the shank frame; the knee assembly having a spring, clutch, means for engaging the clutch; and programmable means for engaging the clutch at a selected angle between the thigh frame and shank frame.

Abstract: Disclosed and claimed herein are spiral torsion springs, non-linear torsion springs, and non-linear torsion spring assemblies. These devices are useful in damping applications, orthotic joint applications and servo control applications.

Abstract: An internet router is implemented as a network fabric of fabric routers and links. The internet router receives data packets from trunk lines or other internet links and analyzes header information in the data packets to route the data packets to output internet links. The line interface also analyzes the header to define a fabric path through the router fabric. The internet packets are broken into flits which are transferred through the router according to a wormhole routing protocol. Flits are stored in fabric routers at storage locations assigned to virtual channels corresponding to destination internet links. The virtual channels and links within the fabric define virtual networks in which congestion in one virtual network is substantially nonblocking to data flow through other virtual networks. Arbitration is performed at each fabric router to assign packets to virtual channels and to assign virtual channels to output fabric links.

Abstract: An Internet router treats plural output ports with a common destination as a composite port. A routing table uses the IP address to determine a composite trunk to which the packet is to be forwarded. A forwarding table identifies a route along a routing fabric within the router to a specific output port of the composite port. Output ports and fabric routes are selected to maintain order within a flow by routing the flow along a single fabric route to a single output trunk. The forwarding table may favor output ports which are nearest to a packet input port, and the forwarding table may be modified to dynamically balance load across the trunks of a composite trunk.

Abstract: In a network router, a tree structure or a sorting network is used to compare scheduling values and select a packet to be forwarded from an appropriate queue. In the tree structure, each leaf represents the scheduling value of a queue and internal nodes of the structure represent winners in comparisons of scheduling values of sibling nodes of the tree structure. CBR scheduling values may first be compared to select a queue and, if transmission from a CBR queue is not timely, a packet may be selected using WFQ scheduling values. The scheduling values are updated to reflect variable packet lengths and byte stuffing in the prior packet. Scheduling may be performed in multiple stages.

Abstract: Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search engine, and SDRAMs share address and control pins to plural search engines on the IC chip. Internal nodes of the tree data structure are duplicated across banks of the SDRAMs to increase bandwidth, and leaf nodes are stored across the SDRAM banks to reduce storage requirements. Within each search engine, data stored in a data register from an SDRAM is compared to a prefix search key stored in a key register. Based on that comparison, an address is calculated to access further tree structure data from the SDRAM. Packet descriptors containing search keys are forwarded to the search engines from an input queue and the search results are forwarded to an output queue, the same packet order being maintained in the two queues.

Abstract: Embodiments of the invention relate to walking/running braces and to devices for enhancing locomotion, specifically human bipedal locomotion. More particularly, it relates to a controlled mechanical device which provides support of the torso via the hip sockets, reduces the metabolic energy associated with walking/running and reduces the incidence of falls caused by insufficient leg thrust. Embodiments of the invention also relates to reducing the strain and metabolic energy consumption associated with walking/running with a heavy backpack or other significant carried load.

Abstract: An internet router is implemented as a network fabric of fabric routers and links. The internet router receives data packets from trunk lines or other internet links and analyzes header information in the data packets to route the data packets to output internet links. The line interface also analyzes the header to define a fabric path through the router fabric. The internet packets are broken into flits which are transferred through the router according to a wormhole routing protocol. Flits are stored in fabric routers at storage locations assigned to virtual channels corresponding to destination internet links. The virtual channels and links within the fabric define virtual networks in which congestion in one virtual network is substantially nonblocking to data flow through other virtual networks. Arbitration is performed at each fabric router to assign packets to virtual channels and to assign virtual channels to output fabric links.

Abstract: Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search engine, and SDRAMs share address and control pins to plural search engines on the IC chip. Internal nodes of the tree data structure are duplicated across banks of the SDRAMs to increase bandwidth, and leaf nodes are stored across the SDRAM banks to reduce storage requirements. Within each search engine, data stored in a data register from an SDRAM is compared to a prefix search key stored in a key register. Based on that comparison, an address is calculated to access further tree structure data from the SDRAM. Packet descriptors containing search keys are forwarded to the search engines from an input queue and the search results are forwarded to an output queue, the same packet order being maintained in the two queues.

Abstract: A router coupled to a plurality of external links transporting data packets to and from the router. Embodiments of the router including a plurality of fabric routers interconnected by fabric links forming or capable of forming a Gamma graph interconnection network. One or more external links are coupled to each fabric router allowing the routing of packets between external links by traversing one or more hops across the fabric links. The Gamma graph interconnection network of the router providing for high port counts and increased bandwidth availability. Furthermore, the use of industry standard buses, such as Infiniband buses, allow for the interconnection of multiple heterogeneous application specific modules to interface and communicate with one another.

Abstract: Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around connections. In preferred embodiments, all nodes supported on each backplane are connected in a single cycle which includes nodes on opposite sides of lower dimension tori. The cycles in adjacent backplanes hop different numbers of nodes.

Abstract: A network is disclosed for interconnecting devices external to the network. Embodiments of the network include a plurality of switching nodes interconnected by links forming or capable of forming a Gamma graph interconnection network. Devices are coupled to the network via a plurality of ports. Furthermore, the network includes a plurality of Infiniband buses with each switching node coupled to at least one of the buses. Each Infiniband bus is capable of supporting a configurable number of ports such that the bandwidth of a port is inversely proportional to the number of ports configured per bus. The Gamma graph interconnection network of the router providing for high port counts and increased bandwidth availability. Furthermore, the use of industry standard buses, such as Infiniband buses, allow for the interconnection of multiple heterogeneous application specific modules to interface and communicate with one another.

Abstract: A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths that provide pass-through electrical paths. The assembly includes two backplanes, a first set of module connectors for electrically connecting modules to one of the backplanes, and a second set of module connectors for electrically connecting modules to the other backplane. The assembly further includes configuration controllers. Each configuration controller selects between end-around electrical paths that electrically connect multiple module connectors of the first set to each other, and pass-through electrical paths that electrically connect module connectors of the first set to module connectors of the second set.

Abstract: An interconnection network, particularly a Gamma graph network, comprising a number of interconnected routers implementing source based and egress based virtual networks in order to prevent tree saturation and deadlock while routing packets. The interconnection network can be used as a fabric within a multi-application switch router, for example. Packets traverse the fabric from any packet source to any packet destination by traversing a source based virtual network associated with a packet source and then by traversing an egress based virtual network associated with a packet destination. By partitioning the fabric into source based virtual networks and egress based virtual networks, the number of control structures required to manage them are reduced as compared with destination based virtual network architectures.

Abstract: An optical data stream is converted to electrical signals which are applied to a time-slot interchanger. The time-slot interchanger recorders the packets or cells of the data stream to correspond to the schedule of an optical switch. The time-slot interchanger may contain a plurality of FIFOs implemented as circular buffers in a single dual port memory. The switch schedule may be determined by the average load between inputs and outputs and may be determined by the number of packets or cells queued from each input or each output in the time-slot interchangers.

Abstract: In a network router, a tree structure or a sorting network is used to compare scheduling values and select a packet to be forwarded from an appropriate queue. In the tree structure, each leaf represents the scheduling value of a queue and internal nodes of the structure represent winners in comparisons of scheduling values of sibling nodes of the tree structure. CBR scheduling values may first be compared to select a queue and, if transmission from a CBR queue is not timely, a packet may be selected using WFQ scheduling values. The scheduling values are updated to reflect variable packet lengths and byte stuffing in the prior packet. Scheduling may be performed in multiple stages.

Abstract: The required length of a route descriptor in a source routing system is obtained by inserting an implied exit field, use of run-length encoding, and use of variable-length encoding. In the variable-length encoding, codes having lesser bits are reserved for preferred directions. Preferred direction may be encoded in the routing header, and it may be implied by the arrival port.

Abstract: A router routes data packets. The router includes input physical channels for incrementally receiving portions of the data packets, and output physical channels. The router further includes data buffers, coupled with the input and output physical channels, for storing the portions of the data packets. The router further includes control circuitry, coupled with the input and output physical channels and the data buffers, for generating virtual channel assignments that assign virtual channels to the data packets, and generating physical channel assignments that assign the output physical channels to the virtual channels. Each of the assignments is generated in response to queued arrival and credit events. The portions of the data packets are forwarded from the data buffers to the output physical channels according to the generate virtual and physical channel assignments.