Abstract: In one embodiment, an apparatus comprises a storage device and a processor. The storage device stores a feature vector index, wherein the feature vector index comprises a sparse-array data structure representing a feature space for a set of labeled feature vectors, wherein the set of labeled feature vectors are assigned to a plurality of classes. The processor is to: receive a query corresponding to a target feature vector; access, via the storage device, a first portion of the feature vector index, wherein the first portion of the feature vector index comprises a subset of labeled feature vectors that correspond to a same portion of the feature space as the target feature vector; determine the corresponding class of the target feature vector based on the subset of labeled feature vectors; and provide a response to the query based on the corresponding class.

Abstract: Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

Abstract: Technologies for software testing include a computing device having persistent memory that includes a platform simulator and an application or other code module to be tested. The computing device generates a checkpoint for the application at a test location using the platform simulator. The computing device executes the application from the test location to an end location and traces all writes to persistent memory using the platform simulator. The computing device generates permutations of persistent memory writes that are allowed by the hardware specification of the computing device simulated by the platform simulator. The computing device replays each permutation from the checkpoint, simulates a power failure, and then invokes a user-defined test function using the platform simulator. The computing device may test different permutations of memory writes until the application's use of persistent memory is validated. Other embodiments are described and claimed.

Abstract: Technologies for software testing include a computing device having persistent memory that includes a platform simulator and an application or other code module to be tested. The computing device generates a checkpoint for the application at a test location using the platform simulator. The computing device executes the application from the test location to an end location and traces all writes to persistent memory using the platform simulator. The computing device generates permutations of persistent memory writes that are allowed by the hardware specification of the computing device simulated by the platform simulator. The computing device replays each permutation from the checkpoint, simulates a power failure, and then invokes a user-defined test function using the platform simulator. The computing device may test different permutations of memory writes until the application's use of persistent memory is validated. Other embodiments are described and claimed.

Abstract: A processing system includes at least one processing unit, at least one bus, and at least one device on the bus. A virtual machine monitor (VMM) in the processing system determines whether a base address register (BAR) of the device specifies a barred region size of less than one page. If the BAR specifies a barred region size of less than one page, the VMM reports to a virtual machine (VM) in the processing system, on behalf of the device, that the BAR specifies a barred region size of at least one page. In one embodiment, the bus comprises a peripheral component interconnect (PCI) bus, such as a PCI Express (PCIe) bus or a PCI Extended (PCI-X) bus. The device may be a video controller, a network interface controller (NIC), or any other suitable device. Other embodiments are described and claimed.

Abstract: Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

Abstract: In some embodiments devices are enabled to run virtual machine workloads directly. Isolation and scheduling are provided between workloads from different virtual machines. Other embodiments are described and claimed.

Abstract: A method, apparatus and system enable a virtual machine manager (“VMM”) to dynamically reassign physical devices from one virtual machine (“VM”) to another. The VMM may generate a message to the VM that currently owns the physical device and inform the device that the physical device is shutting down. The current VM may thereafter idle the physical device, unload the device driver and eject the device. The VMM may then inform another VM that the physical device is available, and the second VM may load the driver for the device.

Abstract: A method, apparatus and system are described for seamlessly sharing I/O devices amongst multiple virtual machines (“VMs”) on a host computer. Specifically, according to one embodiment of the invention, the virtual machine manager (“VMM”) on the host cycles access to the I/O devices amongst the VMs according to a round robin or other such allocation scheme. In order to provide direct access to the devices, the VMM may save the device state pertaining to the currently active VM, store the state in a memory region allocated to the currently active VM, retrieve a device state for a new VM from its memory region and restore the device using the retrieved device state, thus providing the illusion that each VM has direct, full-speed, exclusive access to the I/O device.

Abstract: A processing system includes at least one processing unit, at least one bus, and at least one device on the bus. A virtual machine monitor (VMM) in the processing system determines whether a base address register (BAR) of the device specifies a barred region size of less than one page. If the BAR specifies a barred region size of less than one page, the VMM reports to a virtual machine (VM) in the processing system, on behalf of the device, that the BAR specifies a barred region size of at least one page. In one embodiment, the bus comprises a peripheral component interconnect (PCI) bus, such as a PCI Express (PCIe) bus or a PCI Extended (PCI-X) bus. The device may be a video controller, a network interface controller (NIC), or any other suitable device. Other embodiments are described and claimed.

Abstract: A calibration system for a vision-based automatic writing implement is disclosed. The automatically controlled writing implement is appended to an articulated robot arm. The writing implement draws or writes on a substrate and recognizes what a user draws or writes on the same substrate. The user may move the substrate while drawing, thereby confusing the drawing and recognition processes. Accordingly, a controller draws a target on the substrate initially. Before each drawing or recognition step, the controller uses a digital video camera to find and recognize the target and determine whether the substrate has moved. The target is asymmetrical, such that the controller can determine the orientation as well as the position of the substrate. The controller can then orient its drawing and recognition algorithms to the new location and orientation of the substrate.

Abstract: Creation of a cutting template for a virtual jigsaw puzzle using guide points and a spline-fitting algorithm is described. Guide points that define geometric parameters of a piece of a virtual jigsaw puzzle are selected. A curve is fit to the guide points using a spline-fitting algorithm to define a shape of the puzzle piece.

Abstract: Creation of a cutting template for a virtual jigsaw puzzle using guide points and a spline-fitting algorithm is described. Guide points that define geometric parameters of a piece of a virtual jigsaw puzzle are selected. A curve is fit to the guide points using a spline-fitting algorithm to define a shape of the puzzle piece.

Abstract: A calibration system for a vision-based automatic writing implement is disclosed. The automatically controlled writing implement is appended to an articulated robot arm. The writing implement draws or writes on a substrate and recognizes what a user draws or writes on the same substrate. The user may move the substrate while drawing, thereby confusing the drawing and recognition processes. Accordingly, a controller draws a target on the substrate initially. Before each drawing or recognition step, the controller uses a digital video camera to find and recognize the target and determine whether the substrate has moved. The target is asymmetrical, such that the controller can determine the orientation as well as the position of the substrate. The controller can then orient its drawing and recognition algorithms to the new location and orientation of the substrate.

Abstract: A character good suitable for entertainment and/or educational purposes is disclosed. The character good includes one or more audio and/or video input generation devices that operate to generate audio and/or video inputs responsive to audio sensed and/or scenes observed in the character good's surrounding, to provide the character good with simulated listening and/or visual ability. The generated audio and/or video input signals are forwarded to an external computer for processing. The character good further includes one or more audio and/or electromechanical devices that operate to manifest audio and/or gesture responses under the control of the external computer, to provide the character good with simulated speech and/or gesture ability. The external computer exercises the control responsive to the generated audio and/or video inputs.

Abstract: A computer system with an operating system and a data-processing system running on a host processor, and a receiver. The receiver sends interrupt signals to the operating system after the receiver has received data signals. The operating system establishes interrupt times and passes the interrupt signals to the data-processing system. The data-processing system accesses the data signals from the receiver and only partially processes the data signals during the interrupt times. The operating system also receives clock interrupt signals, which it passes on to the data-processing system. The data-processing system completes the processing of the data signals during the clock interrupt times that the operating system establishes in response to the clock interrupt signals.

Abstract: Management computers of a packet-switched computer network allocate transmission bandwidth for transmissions such as those for conferences between client computers of the network. Callers and callees request bandwidth from their associated managers for transmissions. Managers monitor and allocate bandwidth taking into account whether the transmissions are between local clients or local and external clients. Managers maintain records of active transmissions, but need not maintain lists of client computers with which the managers are associated.

Abstract: A circuit for software performance analysis implements a balanced binary tree in hardware. This circuit consists of a number of "levels", each containing two (sets of) latches, a RAM, and a digital comparator. One of the latches, the data latch, is used to hold the data element being evaluated. The other latch, the results latch, stores partial results based on the comparisons performed on higher levels. The RAM is addressed by the contents of the results latch on the preceding level in combination with the output of the comparator on that same preceding level. The output of the RAM is compared by the digital comparator with the contents of the data latch, to produce an additional bit of results information for the next level. On each level, the RAM is preprogrammed with twice as many midpoint addresses as is the RAM on the preceding level. The outcome of the comparison done on any particular level is used, along with the results from preceding levels, as an address to access a RAM on the next level.