Abstract: An embodiment of a parallel processor apparatus may include a sample pattern selector to select a sample pattern for a pixel, and a sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is different from the first subset. Other embodiments are disclosed and claimed.

Abstract: Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.

Abstract: Systems, apparatuses and methods may provide for technology that determines a position associated with one or more polygons in unresolved surface data and select an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position. Additionally, the unresolved surface data may be resolved at the position in accordance with the selected anti-aliasing sample rate, wherein the selected anti-aliasing sample rate varies across a plurality of pixels. The position may be a bounding box, a display screen coordinate, and so forth.

Abstract: Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.

Abstract: Systems, apparatuses and methods may provide a way to subdivide a patch generated in graphics processing pipeline into sub-patches, and generate sub-patch tessellations for the sub-patches. More particularly, systems, apparatuses and methods may provide a way to diverge tessellation sizes to a configurable size within an interior region of a patch or sub-patches based on a position of each of the tessellations. The systems, apparatuses and methods may determine a number of tessellation factors to use based on one or more of a level of granularity of one or more domains of a scene to be digitally rendered, available computing capacity, or power consumption to compute the number of tessellation factors.

Abstract: Systems, apparatuses and methods may provide a way to monitor, by a process monitor, one or more processing factors of one or more client devices hosting one or more user sessions. More particularly, the systems, apparatuses and methods may provide a way to generate, responsively, a scene generation plan based on one or more of a digital representation of an N dimensional space or at least one of the one or more processing factors, and generate, by a global scene generator, a global scene common to the one or more client devices based on the digital representation of the space. The systems, apparatuses and methods may further provide for performing, by a local scene generator, at least a portion of the global illumination based on one or more of the scene generation plan, or application parameters.

Abstract: Systems, apparatuses, and methods may provide for technology to render and compress stereoscopic graphical data. In one example, the technology identifies, from graphical data associated with a stereoscopic image defined by a first perspective view and a second perspective view, a background region and a foreground region of a graphical scene in the stereoscopic image, renders graphical data of the identified background region for the first perspective view, and compresses the rendered graphical data.

Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a parallel processor apparatus may include a sample pattern selector to select a sample pattern for a pixel, and a sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is different from the first subset. Other embodiments are disclosed and claimed.

Abstract: Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.

Abstract: Systems, apparatuses and methods may provide for technology that determines a position associated with one or more polygons in unresolved surface data and select an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position. Additionally, the unresolved surface data may be resolved at the position in accordance with the selected anti-aliasing sample rate, wherein the selected anti-aliasing sample rate varies across a plurality of pixels. The position may be a bounding box, a display screen coordinate, and so forth.

Abstract: An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.

Abstract: A 3D graphics architecture in which interfaces to memory are combined with pipeline processing. The rendering units are not all connected in a straight-through pipeline relationship: instead the rendering pipeline is “broken,” so that the stream of fragments (e.g. triangles) being processed is parked in memory. This turns out to be surprisingly efficient as a way to separate rendering processes where the workload balance is different. Preferably a first write to memory is performed after transformation and lighting calculations and before double-pass Z-buffering, and a second write to memory is performed before texturing. If Z-buffering or texturing is not being used for a particular rendering task, one or both of the memory interfaces can be switched off for that task. This economizes on memory bandwidth while retaining full flexibility.

Abstract: A set of techniques for rapidly computing a half-plane membership test for successive patches of pixels. By using an inheritance relation to carry forward values already computed at patch boundaries, the computational load for each successive patch is minimized. In a sample embodiment, just one interior point and one new boundary point are computed for each new patch of 64 pixels. Each of the 64 pixels can be described by an offset from one of the 5 reference points (i.e. the one interior point, the one newly computed boundary point, and 3 previously computed boundary points). By exploiting shift and complement relations, only a small number of offsets need to be independently computed (only 10 in this example). Since membership is determined merely by the sign of the relevant half-plane functions being computed, a simple compare between the half-plane function at the reference point and the half-plane function for the relevant offset suffices to evaluate the function's sign for that particular pixel.

Abstract: A 3D graphics architecture in which interfaces to memory are combined with pipeline processing. The rendering units are not all connected in a straight-through pipeline relationship: instead the rendering pipeline is “broken,” so that the stream of fragments (e.g. triangles) being processed is parked in memory. This turns out to be surprisingly efficient as a way to separate rendering processes where the workload balance is different. Preferably a first write to memory is performed after transformation and lighting calculations and before double-pass Z-buffering, and a second write to memory is performed before texturing. If Z-buffering or texturing is not being used for a particular rendering task, one or both of the memory interfaces can be switched off for that task. This economizes on memory bandwidth while retaining full flexibility.

Abstract: A set of techniques for rapidly computing a half-plane membership test for successive patches of pixels. By using an inheritance relation to carry forward values already computed at patch boundaries, the computational load for each successive patch is minimized. In a sample embodiment, just one interior point and one new boundary point are computed for each new patch of 64 pixels. Each of the 64 pixels can be described by an offset from one of the 5 reference points (i.e. the one interior point, the one newly computed boundary point, and 3 previously computed boundary points). By exploiting shift and complement relations, only a small number of offsets need to be independently computed (only 10 in this example). Since membership is determined merely by the sign of the relevant half-plane functions being computed, a simple compare between the half-plane function at the reference point and the half-plane function for the relevant offset suffices to evaluate the function's sign for that particular pixel.

Abstract: A graphics processing unit in which the caching algorithm changes at the end of a line (or alternatively when the data from the beginning of the current line comes up for discard). This avoids the problem of continuous misses at the start of a new line, which can occur when the texture cache is not big enough to hold a full line's worth of data.