Abstract: Embodiments herein relate to a computer which operates in a normal power mode, a full low power mode and a modified low power mode. A power supply unit (PSU) includes main power rails and a standby power rail. An intelligent decision is made as to when to turn on and off the main power rails based on the needs of connected devices such as USB Type-C devices. Power Delivery controllers communicate with the USB devices to determine their power consumption needs, and the total power consumption is aggregated at an embedded controller. If the total exceeds an available power budget, the PSU is controlled to allow for a modified low power mode in which full power is maintained at the main power rails while non-essential internal components are turned off.

Abstract: Power management circuitry may be provided to control a power state of a voltage regulator for providing a regulated voltage to a load, the voltage regulator being operable in at least first and second different power states. The power management circuitry may comprise circuitry to determine output current data relating to an output current to be provided by the voltage regulator to the load. The power management circuitry may comprise circuitry to determine regulated voltage data relating to a regulated voltage to be provided by the voltage regulator to the load. The power management circuitry may comprise circuitry to cause a change in the power state of the voltage regulator from the first power state to the second power state based on a comparison of the determined output current data and power state current threshold data.

Abstract: In some examples, a voltage protection apparatus includes a circuit to compare an input voltage of a processor to a threshold voltage, and to provide a throttle signal to the processor if the input voltage of the processor droops below the threshold voltage. The processor input voltage can then be set to a lower voltage and the processor power can thus be lowered.

Abstract: In some examples, a charging system includes a battery and a power device. The power device is to be coupled in series with the battery in a manner that the power device is not in a system load path. The power device is to operate as a linear voltage regulator to control charging power.

Abstract: Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed.

Abstract: An apparatus may include first circuitry coupled to one or more platform components, the first circuitry operative to receive an unfiltered input voltage signal, compare a first voltage level of the unfiltered input voltage signal to a first reference voltage level, and generate a control signal operative to lower operation power of one or more of the one or more platform components when the first voltage level is less than the first reference voltage level.

Abstract: Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed.

Abstract: Methods and apparatus relating to controlling processor slew rates based on battery charge state/level are described. In one embodiment, logic causes modification to a slew rate of a processor based on at least a charge level of a battery pack. Other embodiments are also disclosed and claimed.

Abstract: An apparatus may include first circuitry coupled to one or more platform components, the first circuitry operative to receive an unfiltered input voltage signal, compare a first voltage level of the unfiltered input voltage signal to a first reference voltage level, and generate a control signal operative to lower operation power of one or more of the one or more platform components when the first voltage level is less than the first reference voltage level.

Abstract: Power gating control architectures. A memory device having at least a memory array and input/output (I/O) lines terminated on the memory device with termination circuitry coupled to receive a termination supply voltage (Vtt) with power gating circuitry to selectively gate the termination supply voltage in response to a power gating control signal (VttControl) is coupled with a processing core coupled with the memory device, the processing core to selectively assert and deassert the VttControl signal.

Abstract: Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal.

Abstract: Methods and apparatus relating to controlling processor slew rates based on battery charge state/level are described. In one embodiment, logic causes modification to a slew rate of a processor based on at least a charge level of a battery pack. Other embodiments are also disclosed and claimed.

Abstract: Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed.

Abstract: An apparatus may comprise a platform power protection circuit to monitor an electric current over a platform input line, the electric current received on the platform input line from a current source, and output an alert signal from a comparator when current output is determined to exceed a current threshold. The apparatus may further include logic to assert a control signal to reduce power consumption in one or more platform components coupled to the platform input line when the alert signal is received. Other embodiments are disclosed and claimed.

Abstract: An apparatus may include first circuitry coupled to one or more platform components, the first circuitry operative to receive an unfiltered input voltage signal, compare a first voltage level of the unfiltered input voltage signal to a first reference voltage level, and generate a control signal operative to lower operation power of one or more of the one or more platform components when the first voltage level is less than the first reference voltage level.

Abstract: Power gating control architectures. A memory device having at least a memory array and input/output (I/O) lines terminated on the memory device with termination circuitry coupled to receive a termination supply voltage (Vtt) with power gating circuitry to selectively gate the termination supply voltage in response to a power gating control signal (VttControl) is coupled with a processing core coupled with the memory device, the processing core to selectively assert and deassert the VttControl signal.

Abstract: In some embodiments, a method, apparatus and system for enabling and disabling voltage regulator controllers are generally presented. In this regard, a sequencer agent is introduced to selectively enable or disable the outputs of voltage regulator controllers in an electronic appliance based at least in part on settings stored in non-volatile memory. Other embodiments are discussed and claimed.

Abstract: Embodiments of the present invention provide for enumerating codecs on a link. A controller asserts a synchronization signal, and drives one or more control lines associated with selected codecs to a first state. The enumeration period is defined by a predefined number of clock periods after de-assertion of the synchronization signal. During the enumeration period, the controller drives the control lines of codecs that are supported to a second state. If the control line for a codec is not pulled to the second state during the enumeration period, that codec will act disabled, ignoring all inputs, and will not participate in any link activity, until the next reset, where it will again look for an assertion of its control line.

Abstract: A method and device are provided for managing a group of electrical devices, e.g., coder/decoders (codecs) in a computer system, including enabling and disabling a primary electrical device. An address ID module assigns a primary address to designate one of the devices as a primary device. The primary device performs certain functions that are only performed by a single device. Other devices are designated as secondary devices. A signal control circuit receives a BIOS-controlled signal as an input, and outputs a presence signal indicating whether the original primary electrical device is enabled or disabled. If the original primary device is disabled, the address ID module designates one of the secondary devices as the new primary device, and the other secondary devices remain secondary. The new primary device performs certain functions of the original primary device.

Abstract: Embodiments of the present invention provide for enumerating codecs on a link. A controller asserts a synchronization signal, and drives one or more control lines associated with selected codecs to a first state. The enumeration period is defined by a predefined number of clock periods after de-assertion of the synchronization signal. During the enumeration period, the controller drives the control lines of codecs that are supported to a second state. If the control line for a codec is not pulled to the second state during the enumeration period, that codec will act disabled, ignoring all inputs, and will not participate in any link activity, until the next reset, where it will again look for an assertion of its control line.