Abstract: Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.

Abstract: Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.

Abstract: On a non-volatile memory circuit, peripheral circuitry generates programming voltages based on parameter values. If parameter values are incorrectly translated into programming voltages, data may be over-programmed, resulting in high bit error rates (BERs). The memory system can monitor the error rates using memory cell voltage distributions for different portions of the memory and look for signatures of such incorrect implementation. For example, by monitoring the BER along word lines that are most prone to error due to incorrectly implemented programming parameters, the memory system can determine if the programming parameters for the corresponding portion of a memory device indicate such anomalous behavior. If such a signature is found, the memory system checks to see whether the programming parameters should be adjusted, such as by comparing the programming parameters used on one die to programming parameters used on another die of the memory system, and adjust the programming parameters accordingly.

Abstract: Apparatuses, systems, methods, and computer program products for dynamically determining boundary word line voltage shift are presented. An apparatus includes an array of non-volatile memory cells and a controller. A controller includes a trigger detection component that is configured to detect a trigger condition associated with a last programmed word line of a partially programmed erase block of an array of non-volatile memory cells. A controller includes a voltage component that is configured to determine a read voltage threshold for a last programmed word line of a partially programmed erase block in response to a trigger condition. A controller includes a voltage shift component that is configured to calculate, dynamically, a read voltage threshold shift for a last programmed word line based on a determined read voltage threshold for the last programmed word line and a baseline read voltage threshold.

Abstract: Apparatuses, systems, methods, and computer program products for dynamically determining boundary word line voltage shift are presented. An apparatus includes an array of non-volatile memory cells and a controller. A controller includes a trigger detection component that is configured to detect a trigger condition associated with a last programmed word line of a partially programmed erase block of an array of non-volatile memory cells. A controller includes a voltage component that is configured to determine a read voltage threshold for a last programmed word line of a partially programmed erase block in response to a trigger condition. A controller includes a voltage shift component that is configured to calculate, dynamically, a read voltage threshold shift for a last programmed word line based on a determined read voltage threshold for the last programmed word line and a baseline read voltage threshold.

Abstract: A storage system and method for reducing XOR recovery time are provided. In one embodiment, a storage system is provides comprising a memory and a controller. The controller is configured to generate a first exclusive-or (XOR) parity for pages of data written to the memory; after the first XOR parity has been generated, determine that there is at least one page of invalid data in the pages of data written to the memory; and generate a second XOR parity for the pages of data that excludes the at least one page of invalid data, wherein the second XOR parity is generated by performing an XOR operation using the first XOR parity and the at least one page of invalid data as inputs. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Certain apparatuses, systems, methods, and computer program products are used for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.

Abstract: A memory device and associated techniques avoid reading memory cells immediately after programming when uncorrectable errors may be present. In one aspect, data is copied from one block to another block and a timer is started after the copying is completed. If a read command is received before the timer has expired, the read operation proceeds by reading the one block. If the read command is received after the timer has expired, the read operation proceeds by reading the another block. This approach is particular suitable when data is copied from single-level cell (SLC) blocks to multi-level cell (MLC) blocks in a folding operation. The duration of the timer can be increased at lower temperatures.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.

Abstract: A storage device with a memory may utilize an optimized read retry operation. A read retry table includes a number of read retry cases with updated read thresholds. The read thresholds in the read retry table may be used to avoid errors caused by shifting of charge levels. The optimization of read retry includes weighting or reordering of the read retry cases in the read retry table. The selection of a read retry case (and corresponding read thresholds) are determined based on the weighting or reordering.

Abstract: A memory device and associated techniques avoid reading memory cells immediately after programming when uncorrectable errors may be present. In one aspect, data is copied from one block to another block and a timer is started after the copying is completed. If a read command is received before the timer has expired, the read operation proceeds by reading the one block. If the read command is received after the timer has expired, the read operation proceeds by reading the another block. This approach is particular suitable when data is copied from single-level cell (SLC) blocks to multi-level cell (MLC) blocks in a folding operation. The duration of the timer can be increased at lower temperatures.

Abstract: A storage device with a memory may modify throttling to reduce cross temperature effects. The decision to throttle may be based on a memory device temperature (i.e. temperature throttling) or may be based on the memory device's health, usage, or performance (e.g. hot count or bit error rate). Temperature throttling may be implemented that considers the memory device's health, usage, or performance (e.g. hot count or bit error rate). Likewise, throttling based on the memory device's health, usage, or performance may utilize the memory device's temperature to optimize throttling time. For example, a test mode matrix (TMM) may be modified to depend on temperature.

Abstract: A storage system and method for temperature throttling for block reading are provided. In one embodiment, a storage system is provided comprising a memory comprising a plurality of word lines and a controller in communication with the memory. The controller is configured to determine whether a temperature of the memory is above a first threshold temperature; and in response to determining that the temperature of the memory is above the first threshold temperature: apply a voltage to the plurality of word lines; and after the voltage has been applied, read one of the plurality of word lines. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A storage system and method for temperature throttling for block reading are provided. In one embodiment, a storage system is provided comprising a memory comprising a plurality of word lines and a controller in communication with the memory. The controller is configured to determine whether a temperature of the memory is above a first threshold temperature; and in response to determining that the temperature of the memory is above the first threshold temperature: apply a voltage to the plurality of word lines; and after the voltage has been applied, read one of the plurality of word lines. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A storage system and method for reducing XOR recovery time are provided. In one embodiment, a storage system is provides comprising a memory and a controller. The controller is configured to generate a first exclusive-or (XOR) parity for pages of data written to the memory; after the first XOR parity has been generated, determine that there is at least one page of invalid data in the pages of data written to the memory; and generate a second XOR parity for the pages of data that excludes the at least one page of invalid data, wherein the second XOR parity is generated by performing an XOR operation using the first XOR parity and the at least one page of invalid data as inputs. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A storage device with a memory may utilize an optimized read retry operation. A read retry table includes a number of read retry cases with updated read thresholds. The read thresholds in the read retry table may be used to avoid errors caused by shifting of charge levels. The optimization of read retry includes weighting or reordering of the read retry cases in the read retry table. The selection of a read retry case (and corresponding read thresholds) are determined based on the weighting or reordering.

Abstract: A storage device with a memory may modify throttling to reduce cross temperature effects. The decision to throttle may be based on a memory device temperature (i.e. temperature throttling) or may be based on the memory device's health, usage, or performance (e.g. hot count or bit error rate). Temperature throttling may be implemented that considers the memory device's health, usage, or performance (e.g. hot count or bit error rate). Likewise, throttling based on the memory device's health, usage, or performance may utilize the memory device's temperature to optimize throttling time. For example, a test mode matrix (TMM) may be modified to depend on temperature.

Abstract: Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.

Abstract: Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1's when the device is powered on. When a sensing operation occurs, the counter is periodically incremented based on a clock. When a next read operation occurs, the value of the counter is cross-referenced to an optimal set of read voltage shifts. Each block of cells may have its own counter, where the counters are incremented using a local or global clock.