Patents by Inventor Philip Rogers Hillier
Philip Rogers Hillier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8103930Abstract: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.Type: GrantFiled: May 27, 2008Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: Wayne Melvin Barrett, Philip Rogers Hillier, III, Joseph Allen Kirscht, Elizabeth A. McGlone
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Patent number: 8082396Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, select a command to send to memory. In an embodiment, the oldest command in a write queue that does not collide with a conflict queue is sent to memory and added to the conflict queue if some or all of the following are true: all of the commands in the read queue collide with the conflict queue, any read command incoming from the processor does not collide with the write queue, the number of commands in the write queue is greater than a first threshold, and all commands in the conflict queue have been present for less than a second threshold. In an embodiment, a command does not collide with a queue if the command does not access the same cache line in memory as the commands in the queue. In this way, in an embodiment, write commands are sent to the memory at a time that reduces the impact on the performance of read commands.Type: GrantFiled: April 28, 2005Date of Patent: December 20, 2011Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Philip Rogers Hillier, III, Joseph Allen Kirscht, Brian T. Vanderpool
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Publication number: 20110261821Abstract: A method and circuit for implementing multiple active paths between source and destination devices in an interconnect system while removing ghost packets, and a design structure on which the subject circuit resides are provided. Each packet includes a generation ID and is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The packets are transmitted from a source interconnect chip source to a destination interconnect chip on the multiple active paths. The generation ID of a received packet is compared with a current generation ID at a destination interconnect chip to validate packet acceptance. The destination interconnect chip uses the ETE sequence numbers to reorder the accepted received packets into the correct order before sending the packets to the destination device.Type: ApplicationFiled: April 21, 2010Publication date: October 27, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Philip Rogers Hillier, III, David Alan Shedivy, Kenneth Michael Valk, Bruce Marshall Walk
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Publication number: 20110228783Abstract: A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.Type: ApplicationFiled: March 19, 2010Publication date: September 22, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William Thomas Flynn, Philip Rogers Hillier, III, David Alan Shedivy, Kenneth Michael Valk
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Patent number: 7970980Abstract: A computer system includes at least one processor, multiple memory modules embodying a main memory, a communications medium for communicating data between the at least one processor and main memory, and memory access control logic which controls the routing of data and access to memory. The communications medium and memory access control logic are designed to accommodate a heterogenous collection of main memory configurations, in which at least one physical parameter is variable for different configurations. The bits of the memory address are mapped to actual memory locations by assigning fixed bit positions to the most critical physical parameters across multiple different module types, and assigning remaining non-contiguous bit positions to less critical physical parameters. In the preferred embodiment, the computer system employs a distributed memory architecture.Type: GrantFiled: December 15, 2004Date of Patent: June 28, 2011Assignee: International Business Machines CorporationInventors: Philip Rogers Hillier, III, Joseph Allen Kirscht, Jamie Randall Kuesel
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Patent number: 7949836Abstract: A memory controller performs a mirror copy function in a way that allows processor accesses to memory to continue during the mirror copy operations that make up the mirror copy function. Data integrity of mirror copy operations is assured by protocols set up in the memory controller. The result is a memory controller that performs a mirror copy function in a way that allows normal processor accesses to memory to be interleaved with mirror copy operations, thereby minimizing the impact on system performance of executing the mirror copy function.Type: GrantFiled: June 10, 2004Date of Patent: May 24, 2011Assignee: International Business Machines CorporationInventors: Philip Rogers Hillier, III, Joseph Allen Kirscht, Elizabeth A. McGlone
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Patent number: 7908443Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.Type: GrantFiled: June 10, 2008Date of Patent: March 15, 2011Assignee: International Business Machines CorporationInventors: Philip Rogers Hillier, III, William Paul Hovis, Joseph Allen Kirscht
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Patent number: 7516270Abstract: A memory controller includes scrub circuitry that performs scrub cycles in a way that does not delay processor reads to memory during the scrub cycle. Atomicity of the scrub operation is assured by protocols set up in the memory controller, not by using an explicit atomic read-correct-write operation. The result is a memory controller that efficiently scrubs memory while minimizing the impact of scrub cycles on system performance.Type: GrantFiled: March 26, 2007Date of Patent: April 7, 2009Assignee: International Business Machines CorporationInventors: Philip Rogers Hillier, III, Joseph Allen Kirscht, Elizabeth A. McGlone
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Publication number: 20090024808Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.Type: ApplicationFiled: June 10, 2008Publication date: January 22, 2009Applicant: International Business Machines CorporationInventors: Philip Rogers Hillier, III, William Paul Hovis, Joseph Allen Kirscht
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Publication number: 20090024807Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.Type: ApplicationFiled: June 10, 2008Publication date: January 22, 2009Applicant: International Business Machines CorporationInventors: Philip Rogers Hillier, III, William Paul Hovis, Joseph Allen Kirscht
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Patent number: 7475202Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.Type: GrantFiled: July 18, 2007Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Philip Rogers Hillier, III, William Paul Hovis, Joseph Allen Kirscht
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Patent number: 7472236Abstract: In a data processing system having a memory control device including at least two mirrored memory ports, a method and computer-readable medium for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling read requestors with memory resources. The received read request is issued only to a specified one of the at least two mirrored memory ports within the memory control device. In response to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, the received read request is issued to an alternate of the at least two mirrored memory ports.Type: GrantFiled: October 30, 2007Date of Patent: December 30, 2008Assignee: International Business Machines CorporationInventors: Philip Rogers Hillier, III, Joseph Allen Kirscht, Elizabeth A. McGlone
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Patent number: 7467260Abstract: An apparatus and method is disclosed for flushing a cache in a computing system. In a multinode computing system a cache in a first node may contain modified data in an address space of a second node. The cache in the first node must be purged prior to shutting down the first node. The computing system uses a random class replacement scheme for the cache. A cache flush routine sets a cache flush mode in a class replace select mechanism, overriding the random class replacement scheme. With the random class replacement scheme overridden, a minimum number of fetches will flush all the cache lines in the cache, each fetch loading the cache with a cache line not already in the cache. No additional delay penalty is incurred in a critical path through which fetches and stores to the cache must pass.Type: GrantFiled: October 8, 2004Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: Duane Arlyn Averill, John Michael Borkenhagen, Philip Rogers Hillier, III
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Patent number: 7426672Abstract: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.Type: GrantFiled: April 28, 2005Date of Patent: September 16, 2008Assignee: International Business Machines CorporationInventors: Wayne Melvin Barrett, Philip Rogers Hillier, III, Joseph Allen Kirscht, Elizabeth A. McGlone
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Publication number: 20080222489Abstract: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.Type: ApplicationFiled: May 27, 2008Publication date: September 11, 2008Applicant: International Business Machines CorporationInventors: Wayne Melvin Barrett, Philip Rogers Hillier, Joseph Allen Kirscht, Elizabeth A. McGlone
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Patent number: 7328315Abstract: In a data processing system having a memory control device including at least two mirrored memory ports, a method, system, and article of manufacture for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling read requestors with memory resources. The received read request is issued only to a specified one of the at least two mirrored memory ports within the memory control device. In response to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, the received read request is issued to an alternate of the at least two mirrored memory ports.Type: GrantFiled: February 3, 2005Date of Patent: February 5, 2008Assignee: International Business Machines CorporationInventors: Philip Rogers Hillier, III, Joseph Allen Kirscht, Elizabeth A. McGlone
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Patent number: 7328317Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.Type: GrantFiled: October 21, 2004Date of Patent: February 5, 2008Assignee: International Business Machines CorporationInventors: Philip Rogers Hillier, III, William Paul Hovis, Joseph Allen Kirscht
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Patent number: 7257686Abstract: A memory controller includes scrub circuitry that performs scrub cycles in a way that does not delay processor reads to memory during the scrub cycle. Atomicity of the scrub operation is assured by protocols set up in the memory controller, not by using an explicit atomic read-correct-write operation. The result is a memory controller that efficiently scrubs memory while minimizing the impact of scrub cycles on system performance.Type: GrantFiled: June 3, 2004Date of Patent: August 14, 2007Assignee: International Business Machines CorporationInventors: Philip Rogers Hillier, III, Joseph Allen Kirscht, Elizabeth A. McGlone
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Patent number: 7096289Abstract: Disclosed is a method for and an apparatus using various factors including system performance feedback data to optimize the time suggested to attempt retry of a request. Among the factors used there is included present system performance, type of request, status of pending action, current number of retries pending, a predefined fixed interval, a pseudo random interval, a random interval, past history of retry requests, heuristically determined interval, and an interval based upon hang detection.Type: GrantFiled: January 16, 2003Date of Patent: August 22, 2006Assignee: International Business Machines CorporationInventors: Jeffrey Douglas Brown, Philip Rogers Hillier
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Patent number: 7013375Abstract: Methods, apparatus, and program product are disclosed for use in a computer system in which one or more multiprocessor nodes comprise the computer system. The methods and apparatus provide for configurable allocation of a memory in a node memory controller. In a single node implementation of the computer system, substantially all of the memory is allocated to a snoop directory used to store directory entries for cache lines used by processors in the node. In computer system implementations having more than one node, the amount of the memory allocated to the snoop directory and the amount of the memory allocated to a remote memory directory is controlled respondent to predetermined sizes respondent to the number of nodes in the computer system.Type: GrantFiled: March 31, 2003Date of Patent: March 14, 2006Assignee: International Business Machines CorporationInventors: John Michael Borkenhagen, Philip Rogers Hillier, III, Russell Dean Hoover