Patents by Inventor Philip S. Bednarz

Philip S. Bednarz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adaptive decision feedback equalizer apparatus for processing information stored on digital storage media
    Patent number: 5430661
    Abstract: Adaptive decision feedback equalizer apparatus for processing information stored on disk or tape media or the like including a data input buffer (34), a gain acquisition circuit (42), a timing acquisition circuit (40) operative to generate timing error signals for controlling the sampling phase of the read signals input to the input buffer, a synchronizing circuit (44) for generating sync detect signals and polarity signals, an FIR filter (36) for generating linear filter output signals, register means (39), feedforward update logic (38) for adjusting the equalizer coefficient signals to develop updated coefficient signals, a dual ported RAM (50) for storing a plurality of the equalizer coefficient signals, feedback logic (48) responsive to the linear filter output signals, equalizer coefficient signals obtained from the RAM, and train data signals, and operative to compute the equalizer error signals and equalizer output signals, feedback update logic (52) for adjusting the values of the coefficient signals
    Type: Grant
    Filed: December 2, 1991
    Date of Patent: July 4, 1995
    Assignee: Board of Trustees Leland Stanford, Jr. University
    Inventors: Kevin D. Fisher, William L. Abbott, John M. Cioffi, Philip S. Bednarz
  • Adaptive decision feedback equalizer apparatus for processing information stored on digital storage media
    Patent number: 5132988
    Abstract: Adaptive decision feedback equalizer apparatus for processing information stored on disk or tape media or the like including a data input buffer (34), a gain acquisition circuit (42), a timing acquisition circuit (40) operative to generate timing error signals for controlling the sampling phase of the read signals input to the input buffer, a synchronizing circuit (44) for generating sync detect signals and polarity signals, an FIR filter (36) for generating linear filter output signals, register means (39), feedforward update logic (38) for adjusting the equalizer coefficient signals to develop undated coefficient signals, a dual ported RAM (50) for storing a plurality of the equalizer coefficient signals, feedback logic (48) responsive to the linear filter output signals, equalizer coefficient signals obtained from the RAM, and train data signals, and operative to compute the equalizer error signals and equalizer output signals, feedback update logic (52) for adjusting the values of the coefficient signals
    Type: Grant
    Filed: December 3, 1990
    Date of Patent: July 21, 1992
    Assignee: Board of Trustees, Leland Stanford Jr. University
    Inventors: Kevin D. Fisher, William L. Abbott, John M. Cioffi, Philip S. Bednarz