Abstract: The present disclosure generally provides for a method of prioritizing clock domains for testing an integrated circuit (IC) design. The method can include: assigning each of a plurality of multi-tested clock domains (MTCDs) and a plurality of test experiments (TEs) to one of a plurality of speed priority groups (SPGs), wherein the assigning includes: creating a new SPG having a priority value of n+1, wherein n represents the number of previously created SPGs; assigning a first MTCD corresponding to at least two of the plurality of TEs, the first MTCD not being previously assigned to an SPG, to the new SPG; and assigning each TE corresponding to the first MTCD, each of the assigned TEs not being previously assigned to an SPG, to the new SPG; and performing each of the plurality of TEs on the IC design in order from lowest priority value to highest priority value.

Abstract: The present disclosure generally provides for a method of prioritizing clock domains for testing an integrated circuit (IC) design. The method can include: assigning each of a plurality of multi-tested clock domains (MTCDs) and a plurality of test experiments (TEs) to one of a plurality of speed priority groups (SPGs), wherein the assigning includes: creating a new SPG having a priority value of n+1, wherein n represents the number of previously created SPGs; assigning a first MTCD corresponding to at least two of the plurality of TEs, the first MTCD not being previously assigned to an SPG, to the new SPG; and assigning each TE corresponding to the first MTCD, each of the assigned TEs not being previously assigned to an SPG, to the new SPG; and performing each of the plurality of TEs on the IC design in order from lowest priority value to highest priority value.

Abstract: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

Abstract: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

Abstract: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

Abstract: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

Abstract: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

Abstract: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.