Abstract: An integrated circuit having boundary-scan facilities in accordance with IEEE Standard 1149.1, has its boundary scan chain configured to permit fault insertion testing of diagnostic and maintenance software. Each Scan cell includes storage devices for storing a pair of bits of a binary vector shifted into the boundary scan chain. One bit comprises faulty data and the other bit serves to control application of the faulty data by the scan cell. A system incorporating such integrated circuits includes a controller for controlling the IEEE test interface to shift the binary vector into the boundary scan chain, and diagnostic and maintenance software for diagnosing the faults introduced into the integrated circuits.

Abstract: In a so-called "scan-design" arrangement for testing integrated circuits, whether at the device level or at system level, problems associated with the storage and handling of vast amounts of data from increasingly complex devices are addressed by testing a pair of identical integrated circuits simultaneously and using the binary vector generated by scanning one of these integrated circuits as the reference against which to compare the binary vector produced by scanning the other integrated circuit. A plurality of "scan-designed" integrated circuits may be connected in series, possibly in a ring, and each compared with its predecessor. Zero-display coupling across each device may be employed to allow each successive integrated circuit to be compared with the same reference circuit in the chain or ring.

Abstract: In order to provide for clocking master/slave flip-flops in complex circuits by means of non-overlapping two-phase clocks, a clock generator for providing two clocks signals for use with two-phase flip-flops, comprises a settable latch and a gating device. The settable latch has a data input connected to a reference source, a set input connected to receive one of the two clock signals and a clock input connected to receive the other of the two clock signals. The gating device has one input connected to receive such one of the two clock signals and a second input connected to the output of the settable latch. The output of the gating device, which corresponds to the other of the two clock signals, is connected to the clock input of the settable latch, the arrangement being such that when the settable latch has been set by a transition of the one clock signal resetting of the settable latch is enabled by the other clock signal.