Patents by Inventor Philip Tai

Philip Tai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230340529
    Abstract: Aspects of the disclosure relate to compositions and methods for expressing anti-Vascular endothelial cell growth factor (VEGF) agent in a cell or subject. In some embodiments, the disclosure provides rAAVs comprising a capsid protein (e.g., AAV2 variants, AAV2/3 hybrid variants, AAV8 variants, etc.), and a transgene encoding an anti-VEGF agent (e.g., KH902) and one or more regulatory sequences. In some embodiments, compositions described herein are useful for treating subjects having diseases associated with angiogenesis or aberrant VEGF activity/signaling.
    Type: Application
    Filed: September 2, 2021
    Publication date: October 26, 2023
    Applicant: University of Massachusetts
    Inventors: Guangping Gao, Philip Tai, Claudio Punzo, Haijiang Lin
  • Publication number: 20080066026
    Abstract: A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing estimates of conductance of vias and wire segments in the form of conductance matrix G; and preparing estimates of current I at each intersection based on power consumed by surrounding circuitry, and current vector “I” and conductance matrix “G” are used to solve for voltage drop ?V, in a matrix equation G?V=I, and the voltage drop is displayed, to allow a human to make changes in the design. Pins of unconnected hard macros are temporarily connected to their closest wires, and current therethrough is included in the estimates.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 13, 2008
    Applicant: Synopsys, Inc.
    Inventors: Philip Tai, Yi-Min Jiang, Sung-Hoon Kwon
  • Publication number: 20080052649
    Abstract: A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing estimates of conductance of vias and wire segments in the form of conductance matrix G; and preparing estimates of current I at each intersection based on power consumed by surrounding circuitry, and current vector “I” and conductance matrix “G” are used to solve for voltage drop ?V, in a matrix equation G?V=I, and the voltage drop is displayed, to allow a human to make changes in the design. Pins of unconnected hard macros are temporarily connected to their closest wires, and current therethrough is included in the estimates.
    Type: Application
    Filed: October 30, 2007
    Publication date: February 28, 2008
    Applicant: Synopsys, Inc.
    Inventors: Philip Tai, Yi-Min Jiang, Sung-Hoon Kwon
  • Publication number: 20060095870
    Abstract: A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing estimates of conductance of vias and wire segments in the form of conductance matrix G; and preparing estimates of current I at each intersection based on power consumed by surrounding circuitry, and current vector “I” and conductance matrix “G” are used to solve for voltage drop ?V, in a matrix equation G?V=I, and the voltage drop is displayed, to allow a human to make changes in the design. Pins of unconnected hard macros are temporarily connected to their closest wires, and current therethrough is included in the estimates.
    Type: Application
    Filed: October 29, 2004
    Publication date: May 4, 2006
    Inventors: Philip Tai, Yi-Min Jiang, Sung-Hoon Kwon
  • Publication number: 20060095881
    Abstract: A power pad synthesizer automatically proposes locations of pads that are to carry power in an integrated circuit design. Specifically, a computer is programmed to prepare the plan in at least two stages as follows. In a first stage, a number of pads are proposed around a periphery of the IC design such that an attribute (e.g. maximum voltage drop) satisfies a predetermined condition (e.g. below a user-specified limit that's scaled up by a predetermined amount). In a second stage, the computer automatically identifies a specific location in the design for having an attribute value that satisfies another predetermined condition (e.g. interior location of maximum voltage drop or peripheral location of maximum current), and automatically proposes one or more additional pads at one or more peripheral locations that are identified by a predetermined rule based on the identified specific location (e.g. having the same x-coordinate or the same y-coordinate).
    Type: Application
    Filed: October 29, 2004
    Publication date: May 4, 2006
    Inventors: Sung-Hoon Kwon, Philip Tai, Yi-Min Jiang