Abstract: An apparatus for measuring a time interval between a start signal edge and a stop signal edge provides a stable clock signal as input to a delay line formed by a series of similar logic gates. The output signal of the last gate of the series is phase locked to the clock signal by adjusting a bias signal controlling the switching speed of all gates. The clock signal and the output signal of each gate form a set of phase distributed periodic timing signals applied to a start time measurement unit (TMU) and a similar stop TMU. The start TMU counts edges of one of the timing signals occurring between an edge of an arming signal and the start signal edge and generates output data representing a time delay between the arming signal and the start signal edge. The data represents the start delay as a whole and fractional number of clock signal periods by conveying the counter output and by indicating which of the timing signals had an edge most closely following the start signal edge.

Abstract: A pattern generator for an integrated circuit tester includes an instruction memory storing addressable instructions (INST) and reading out each instruction when addressed by an address (ADDR) supplied as input thereto. An instruction processor receives each instruction read out of the instruction memory and alters the address input to the instruction memory in accordance with the received instruction so that the instruction memory reads out a next instruction. The instruction processor, which includes a conventional return address stack, is capable of executing conventional address increment, call and return instructions. The instruction processor is also capable of executing a temporary return instruction (TEMP) by incrementing its current address output to produce a new return address, by setting its address output to the value of a return address previously saved in the stack, by popping the saved return address from the stack, and by pushing the new return address onto the stack.

Abstract: An integrated circuit (IC) tester organizes an IC test into a succession of test cycles, each test cycle being subdivided into four segments. The tester includes a separate tester channel for carrying out a test activity at each IC pin during each segment of the test cycle. The tester also includes a separate pattern generator for each channel. Each pattern generator concurrently generates four vectors at the start of each test cycle. Each vector tells the channel what activity it is to carry out during a separate segment of the test cycle. Each pattern generator includes a low-speed vector memory storing large blocks of vectors at each address and a cache memory system for caching blocks of vectors read out of the vector memory at a low frequency and then reading vectors out in sets of 16 at the higher test cycle frequency. A vector alignment circuit selects from among the cache memory output vectors to provide the four vectors to the channel for the test cycle.

Abstract: An algorithmic pattern generator produces an output data value during each cycle of a clock signal. The pattern generator includes an addressable instruction memory reading out an instruction during each clock signal cycle. A memory controller normally increments the instruction memory's address during each clock signal cycle, but may jump to another address N+1 clock signal cycles after receiving a CALL, RETURN, REPEAT or BRANCH command from an instruction processor. The instruction processor normally executes the instruction read out of the instruction memory during each clock signal cycle and provides a data field included in the executed instruction as the pattern generator's output data. Other fields of the instruction reference a command the instruction processor sends to the memory controller.

Abstract: A timing signal generator adjustably times successive pulses of an output timing signal. The generator receives input data before each output pulse and controls the timing of that output pulse in accordance with the input data. The generator includes a circuit providing a set of 2N phase signals frequency locked to a reference clock signal but evenly distributed in phase. First and second selectors each sample the data once during each cycle of the clock signal. The sampled data tells the first selector whether it is to produce a first output signal during the next clock signal cycle and, if so, which of the first N phase signals the first selector is to select for controlling timing of edges of the first output signal. The sampled data also tells the second selector whether it is to produce a second output signal during a next clock signal cycle and, if so, which of the second N phase signals the second selector is to select for controlling the second output signal.