Abstract: A pass-through connector includes a first socket connector to connect to a first device, where the first socket connector includes a first set of pins to connect to first contacts on the first device, and a second socket connector to connect to a second device, where the second socket connector includes a second set of pins to directly connect to the first set of pins within the pass-through connector, and a third set of pins to connect to a bus external to the pass-through connector. The second set of pins are to connect second contacts on the second device to the first contacts on the first device, and the third set of pins are to connect third contacts on the second device to the bus.

Abstract: A segmented algorithmic pattern generator engine producing a test signal pattern made of vectors divided into fully definable segments. The engine allows defining processing controls to allow offsets of individual vectors relative to one another and defining additional pattern control formats. Also provided are reducing the pattern format depths in defining counter dimensions within each segment. Single vectors or vector group sequences may be defined at any point as well. The system allows the user control of the pattern generator to compensate for tool and/or device under test latency timing issues. Inputs may be combined and processed into one contiguous pattern of vectors which are definable by the user.

Abstract: A segmented algorithmic pattern generator engine producing a test signal pattern made of vectors divided into fully definable segments. The engine allows defining processing controls to allow offsets of individual vectors relative to one another and defining additional pattern control formats. Also provided are reducing the pattern format depths in defining counter dimensions within each segment. Single vectors or vector group sequences may be defined at any point as well. The system allows the user control of the pattern generator to compensate for tool and/or device under test latency timing issues. Inputs may be combined and processed into one contiguous pattern of vectors which are definable by the user.

Abstract: A segmented algorithmic pattern generator engine producing a test signal pattern made of vectors divided into fully definable segments. The engine allows defining processing controls to allow offsets of individual vectors relative to one another and defining additional pattern control formats. Also provided are reducing the pattern format depths in defining counter dimensions within each segment. Single vectors or vector group sequences may be defined at any point as well. The system allows the user control of the pattern generator to compensate for tool and/or device under test latency timing issues. Inputs may be combined and processed into one contiguous pattern of vectors which are definable by the user.

Abstract: A segmented algorithmic pattern generator engine producing a test signal pattern made of vectors divided into fully definable segments. The engine allows defining processing controls to allow offsets of individual vectors relative to one another and defining additional pattern control formats. Also provided are reducing the pattern format depths in defining counter dimensions within each segment. Single vectors or vector group sequences may be defined at any point as well. The system allows the user control of the pattern generator to compensate for tool and/or device under test latency timing issues. Inputs may be combined and processed into one contiguous pattern of vectors which are definable by the user.

Abstract: Hardware tester and burn-in tools are emulated by providing a user-specified nested sequence of counters, logical combination of the counter outputs and generation of corresponding vectors for application to exercise an integrated circuit device. The vectors are generated in accordance with user-specified parameters and stored in static random access memory until called for application to the integrated circuit. The parameters, preferably specified through use of a graphic user interface, provide an extremely compressed representation of the vectors themselves. Provision is made to accommodate any of a plurality of waveform conventions directly in the vector. An interface table is preferably used to arbitrarily allocate bits of the vector to pins of the integrated circuit device and any of a plurality of clock signals and phases can be provided to any pin. Sequences of vectors may also be generated for each combination of counter output states in accordance with desired memory functions.