Abstract: An electronic control unit suitable for a motorcycle provides diagnostic support, tachometer drive and warning lamp drive all multiplexed onto one pin and driven by a single driver circuit. In a diagnostics mode, the pin is connected to diagnostic equipment. When a diagnostic test has been completed, a tachometer drive signal is output on the pin, the drive signal having a duty cycle set high enough to illuminate the warning lamp if a fault condition is detected by on-board sensors. By combining multiple functions onto a single pin with a single driver circuit, the cost of implementing an engine control unit may be reduced compared with existing arrangements which require separate pins and drivers for each function.

Abstract: An electronic control unit suitable for a motorcycle provides diagnostic support, tachometer drive and warning lamp drive all multiplexed onto one pin and driven by a single driver circuit. In a diagnostics mode, the pin is connected to diagnostic equipment. When a diagnostic test has been completed, a tachometer drive signal is output on the pin, the drive signal having a duty cycle set high enough to illuminate the warning lamp if a fault condition is detected by on-board sensors. By combining multiple functions onto a single pin with a single driver circuit, the cost of implementing an engine control unit may be reduced compared with existing arrangements which require separate pins and drivers for each function.

Abstract: Systems, methods, and computer program products are provided for managing the processing of a financial payment and, more specifically managing the processing of a financial payment in a comprehensive payment hub environment that provides for payment processing, including payment route determination, irrespective of the payment input channel. In accordance with embodiments herein disclosed, managing the processing of the payment includes automatically determining the payment processes and automatically determining the arrangement of the payment processes. As such, the methods, systems, and computer program products herein described provide for an efficient and cost-effective approach to processing payments.

Abstract: Systems, methods, and computer program products are provided for conducting comprehensive payment processing of all payment requests regardless of the payment request channel. Payment requests are transformed from the initial format to a standardized format, which allows for the occurrence of further comprehensive payment processing, referred to herein as payment hub processing. Once the payment request has undergone necessary payment hub processing, the request undergoes further transformation/conversion from the standardized format to a target clearing format. In one embodiment of the invention, the processing hub provides for determining the clearing or remittance channel based on payment routing rules, which may take into account cost, time, risk and any other payment factors.

Abstract: Systems, methods, and computer program products are provided for optimizing routing of financial payments by determining routing on a per-payment transaction basis based on one or more routing rules. The routing rules take into account payment factors such as, but not limited to, cost of payment processing, time for payment processing, risk/quality of payment processing, remittance requirements and/or the destination of the payment. From the payor or payee perspective, payor-defined or payee-defined payment attributes associated with these or other payment factors can be predefined in a payor/payee profile or dynamically defined proximate to the time at which the payment request is initiated. In this regard, present embodiments serve to create a payment process that is beneficial, in terms of cost, timeliness, quality and the like, to both the payor, the payee and financial institution handling payment processing.

Abstract: Systems, methods, and computer program products are provided for managing the processing of a financial payment and, more specifically managing the processing of a financial payment in a comprehensive payment hub environment that provides for payment processing, including payment route determination, irrespective of the payment input channel. In accordance with embodiments herein disclosed, managing the processing of the payment includes automatically determining the payment processes and automatically determining the arrangement of the payment processes. As such, the methods, systems, and computer program products herein described provide for an efficient and cost-effective approach to processing payments.

Abstract: Systems, methods, and computer program products are provided for conducting comprehensive payment processing of all payment requests regardless of the payment request channel. Payment requests are transformed from the initial format to a standardized format, which allows for the occurrence of further comprehensive payment processing, referred to herein as payment hub processing. Once the payment request has undergone necessary payment hub processing, the request undergoes further transformation/conversion from the standardized format to a target clearing format. In one embodiment of the invention, the processing hub provides for determining the clearing or remittance channel based on payment routing rules, which may take into account cost, time, risk and any other payment factors.

Abstract: Systems, methods, and computer program products are provided for improving foreign currency exchange processing of financial payment requests and, more specifically improving the bid/ask spread in foreign currency exchange so as to increase the profitability realized by the financial institution processing the payment. In accordance with embodiments herein disclosed, international financial payment requests are pooled together based on currency type and payment time requirements to provide for better exchange rates.

Abstract: One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

Abstract: A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type different from the first conductivity type. The method further includes forming a dielectric layer over at least a portion of the first substrate region and at least a portion of the second substrate region. The method further includes forming a metal-containing gate layer over at least a portion of the dielectric layer overlying the first substrate region. The method further includes introducing dopants into at least a portion of the first substrate region through the metal-containing gate layer.

Abstract: A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

Abstract: A device structure and method for forming the device structure has a semiconductor substrate with an overlying first metal oxide layer, an overlying intermediate layer with a first metal and either nitrogen or carbon, and an overlying second metal oxide layer. Oxygen is then provided to the intermediate layer. The oxygen has the effect of changing the intermediate layer from a conducting layer to a dielectric layer. A final device may then be formed, for example, by forming a gate and two current electrodes.

Abstract: One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

Abstract: A mixture of materials can be used within a layer of an electronic device to improve electrical and physical properties of the layer. In one set of embodiments, the layer can be a dielectric layer, such as a gate dielectric layer or a capacitor dielectric layer. The dielectric layer can include O, and two or more dissimilar metallic elements. In one specific embodiment, two dissimilar elements may have the same single oxidation state and be miscible within each other. In one embodiment, the dielectric layer can include an alloy of (HfO2)(1-x)(ZrO2)x, wherein x is between 0 and 1. Each of Hf and Zr has a single oxidation state of +4. Other combinations are possible. Improved electrical and physical properties can include better control over grain size, distribution of grain sizes, thickness of the layer across a substrate, improved carrier mobility, threshold voltage stability, or any combination thereof.

Abstract: A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

Abstract: In one embodiment, metal boride (MBx), metal carbide (MCx), metal carbo-nitrides (MCxNy), metal boro-carbide (MBxCy), metal boro-nitride (MBxNy) or metal boro-carbo-nitride (MBxCyNz), wherein the metal is a transition metal (Group III-XII of the periodic chart) may be suitable as NMOS gate electrode materials. Such materials, such as TaC and LaB6, can be formed to have work functions that are within approximately 4-4.3 eV, which is desirable for NMOS transistors. In addition, the amount of carbon or nitrogen can be adjusting the amount of carbon or nitrogen in the precursor to achieve a predetermined metal work function.

Abstract: A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies.

Abstract: The present invention relates to a method to locate particles of a predetermined species within a solid, more specifically to form an oxy-nitride dielectric for VLSI applications. A layer (18) of a substance (YZ) is formed upon a solid (10) and a chemical reaction is performed between the substance (YZ) and a gas (X), thereby releasing particles (Z) of a predetermined species which incorporate into the solid (10). This method is used, for example, to form an oxy-nitride dielectric by incorporating nitrogen within a silicon oxide layer (28′).