Abstract: A circuit arrangement with standby mode minimizing power and/or current consumption having a mains AC power supply terminals and an active circuit capable of converting said mains AC power to lower voltage DC levels for operating in an active mode or in a standby mode as required by an appliance such that the selection of the current sensing resistor value for said current sensing resistor limits the maximum peak current through the FET so that the current sensing resistor arrangement is capable of providing significant increases in a steeper rise time of the current at around mains AC power supply zero crossing, so that current is pulled high while the mains AC power supply voltage is low.

Abstract: A circuit arrangement with standby mode minimising power and/or current consumption having a mains AC power supply terminals and an active circuit capable of converting said mains AC power to lower voltage DC levels for operating in an active mode or in a standby mode as required by an appliance such that the selection of the current sensing resistor value for said current sensing resistor limits the maximum peak current through the FET so that the current sensing resistor arrangement is capable of providing significant increases in a steeper rise time of the current at around mains AC power supply zero crossing, so that current is pulled high while the mains AC power supply voltage is low.

Abstract: A bus buffer can include a data buffer and a clock signal buffer. The data buffer for can include two symmetrical buffer circuits with an output signal that can follow the input voltage to provide bi-directional buffer action for a data path of the bus buffer. The clock buffer can operate in a forward or reverse direction, where the signal direction for the clock signal path in the bus buffer can be controlled with a direction input. The bus buffer can also include an enable circuit for enabling the data path and the clock signal path.

Abstract: A bus buffer can include a data buffer and a clock signal buffer. The data buffer for can include two symmetrical buffer circuits with an output signal that can follow the input voltage to provide bi-directional buffer action for a data path of the bus buffer. The clock buffer can operate in a forward or reverse direction, where the signal direction for the clock signal path in the bus buffer can be controlled with a direction input. The bus buffer can also include an enable circuit for enabling the data path and the clock signal path.