Patents by Inventor Philip V. Kaszuba

Philip V. Kaszuba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10580615
    Abstract: Disclosed are a system and method, wherein, during manufacturing of integrated circuit chips on a semiconductor wafer, an in-line optical inspection is performed to acquire a two-dimensional (2D) image of an area of the semiconductor wafer and to confirm and classify a defect in the area. The 2D image is then converted into a virtual three-dimensional (3D) image. To ensure that the 3D image is accurate, techniques are employed to determine the topography of the surface shown in the 2D image based on material-specific image intensity information and, optionally, to filter out any edge effects that result in anomalies within the 3D image. The resulting 3D image is usable for performing an in-line failure analysis to determine a root cause of a defect. Such an in-line failure analysis can be performed significantly faster than any off-line failure analysis and, thus, allows for essentially real-time advanced process control (APC).
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kok Hin Teo, Jay A. Mody, Jeffrey B. Riendeau, Philip V. Kaszuba, Jian Qiu
  • Publication number: 20190279840
    Abstract: Disclosed are a system and method, wherein, during manufacturing of integrated circuit chips on a semiconductor wafer, an in-line optical inspection is performed to acquire a two-dimensional (2D) image of an area of the semiconductor wafer and to confirm and classify a defect in the area. The 2D image is then converted into a virtual three-dimensional (3D) image. To ensure that the 3D image is accurate, techniques are employed to determine the topography of the surface shown in the 2D image based on material-specific image intensity information and, optionally, to filter out any edge effects that result in anomalies within the 3D image. The resulting 3D image is usable for performing an in-line failure analysis to determine a root cause of a defect. Such an in-line failure analysis can be performed significantly faster than any off-line failure analysis and, thus, allows for essentially real-time advanced process control (APC).
    Type: Application
    Filed: March 6, 2018
    Publication date: September 12, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Kok Hin Teo, Jay A. Mody, Jeffrey B. Riendeau, Philip V. Kaszuba, Jian Qiu
  • Patent number: 7944550
    Abstract: A method of detecting local mechanical stress in integrated devices is provided, the method comprising: enabling the detection of a photovoltage difference between a scan probe device and a surface portion of an integrated device, the scan probe device being configured to deflect in response to the photovoltage difference; measuring the deflection of the scan probe device in response to the photovoltage difference between the scan probe device and the surface portion of the integrated device; and calculating a local stress level within the integrated device by determining a local work function of the surface portion of the integrated device based upon the deflection of the scan probe device.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: May 17, 2011
    Assignee: International Business Machines Corporation
    Inventors: Lloyd Bumm, Daminda Dahayanaka, Philip V. Kaszuba, Leon Moszkowicz, James A. Slinkman
  • Patent number: 7812347
    Abstract: A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure from the substrate so as to reveal an imprint of the removed bottom surface of the structure in a top surface of the substrate. The imprint can then be imaged using an atomic force microscope (AFM). The image can be used to measure the bottom surface of the structure.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: October 12, 2010
    Assignee: International Business Machines Corporation
    Inventors: George W. Banke, Jr., Andrew Deering, Philip V. Kaszuba, Leon Moszkowicz, James Robert, James A. Slinkman
  • Patent number: 7671604
    Abstract: Disclosed is a fault isolation and measurement system that provides multiple near-field scanning isolation techniques on a common platform. The system incorporates the use of a specialized holder to supply electrical bias to internal circuit structures located within an area of a device or material. The system further uses a multi-probe assembly. Each probe is mounted to a support structure around a common reference point and is a component of a different measurement or fault isolation tool. The assembly moves such that each probe can obtain measurements from the same fixed location on the device or material. The relative positioning of the support structure and/or the holder can be changed in order to obtain measurements from multiple same fixed locations within the area. Additionally, the system uses a processor for providing layered images associated with each signal and for precisely aligning those images with design data in order to characterize, or isolate fault locations within the device or material.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: March 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Philip V. Kaszuba, Theodore M. Levin, David P. Vallett
  • Publication number: 20090219508
    Abstract: A method of detecting local mechanical stress in integrated devices is provided, the method comprising: enabling the detection of a photovoltage difference between a scan probe device and a surface portion of an integrated device, the scan probe device being configured to deflect in response to the photovoltage difference; measuring the deflection of the scan probe device in response to the photovoltage difference between the scan probe device and the surface portion of the integrated device; and calculating a local stress level within the integrated device by determining a local work function of the surface portion of the integrated device based upon the deflection of the scan probe device.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 3, 2009
    Inventors: Lloyd Bumm, Daminda Dahayanaka, Philip V. Kaszuba, Leon Moszkowicz, James A. Slinkman
  • Patent number: 7511510
    Abstract: Disclosed is a fault isolation and measurement system that provides multiple near-field scanning isolation techniques on a common platform. The system incorporates the use of a specialized holder to supply electrical bias to internal circuit structures located within an area of a device or material. The system further uses a multi-probe assembly. Each probe is mounted to a support structure around a common reference point and is a component of a different measurement or fault isolation tool. The assembly moves such that each probe can obtain measurements from the same fixed location on the device or material. The relative positioning of the support structure and/or the holder can be changed in order to obtain measurements from multiple same fixed locations within the area. Additionally, the system uses a processor for providing layered images associated with each signal and for precisely aligning those images with design data in order to characterize, or isolate fault locations within the device or material.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: March 31, 2009
    Assignee: International Business Machines Corporation
    Inventors: Philip V. Kaszuba, Theodore M. Levin, David P. Vallett
  • Patent number: 7507591
    Abstract: A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure from the substrate so as to reveal an imprint of the removed bottom surface of the structure in a top surface of the substrate. The imprint can then be imaged using an atomic force microscope (AFM). The image can be used to measure the bottom surface of the structure.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: March 24, 2009
    Assignee: International Business Machines Corporation
    Inventors: George W. Banke, Jr., Andrew Deering, Philip V. Kaszuba, Leon Moszkowicz, James Robert, James A. Slinkman
  • Publication number: 20080238457
    Abstract: Disclosed is a fault isolation and measurement system that provides multiple near-field scanning isolation techniques on a common platform. The system incorporates the use of a specialized holder to supply electrical bias to internal circuit structures located within an area of a device or material. The system further uses a multi-probe assembly. Each probe is mounted to a support structure around a common reference point and is a component of a different measurement or fault isolation tool. The assembly moves such that each probe can obtain measurements from the same fixed location on the device or material. The relative positioning of the support structure and/or the holder can be changed in order to obtain measurements from multiple same fixed locations within the area. Additionally, the system uses a processor for providing layered images associated with each signal and for precisely aligning those images with design data in order to characterize, or isolate fault locations within the device or material.
    Type: Application
    Filed: May 7, 2008
    Publication date: October 2, 2008
    Applicant: International Business Machines Corporation
    Inventors: Philip V. Kaszuba, Theodore M. Levin, David P. Vallett
  • Publication number: 20080157077
    Abstract: A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure from the substrate so as to reveal an imprint of the removed bottom surface of the structure in a top surface of the substrate. The imprint can then be imaged using an atomic force microscope (AFM). The image can be used to measure the bottom surface of the structure.
    Type: Application
    Filed: March 7, 2008
    Publication date: July 3, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: G. W. Banke, Andrew Deering, Philip V. Kaszuba, Leon Moszkowicz, James Robert, James A. Slinkman
  • Patent number: 7205237
    Abstract: Apparatus for exposure and probing of features in a semiconductor workpiece includes a hollow concentrator for covering a portion of the workpiece connected by a gas conduit to a supply of etchant gas. A stage supports and positions the semiconductor workpiece. Control means moves the stage and the semiconductor workpiece to the series of positions sequentially. An energy beam source directs a focused energy beam through an aperture through the concentrator onto a region on the surface of the workpiece in the presence of the etchant gas. The control means moves the stage to a series of positions with respect to the concentrator and the energy beam to direct the energy beam in the presence of the etchant gas to expose a series of regions on the surface of the semiconductor workpiece positioned below the hollow interior space of the concentrator, sequentially.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: April 17, 2007
    Assignee: International Business Machines Corporation
    Inventors: Andrew Deering, Terence L. Kane, Philip V. Kaszuba, Leon Moszkowicz, Carmelo F. Scrudato, Michael Tenney
  • Patent number: 6198300
    Abstract: A micromechanical sensor probe for a scanned-probe tool includes a silicon cantilever and a silicon tip physically attached to the cantilever. The micromechanical sensor probe has a coating of a refractory metal silicide formed at least on the tip. Titanium silicide is preferred. The probe also has a layer of refractory metal nitride formed entirely over the refractory metal silicide.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: March 6, 2001
    Assignee: International Business Machines Corporation
    Inventors: Lambert A. Doezema, Philip V. Kaszuba, Leon Moszkowicz, James M. Never, James A. Slinkman
  • Patent number: 6139759
    Abstract: A micromechanical sensor probe for a scanned-probe tool comprising a silicon probe and a coating of a refractory metal silicide formed at least on the tip of the probe. Titanium silicide is preferred. A method for manufacturing such a probe includes the steps of, first, providing a silicon cantilever and tip combination and, second, forming a refractory metal silicide on at least the tip of the cantilever and tip combination. This second step of the method includes removing any remnant oxide from the tip, stabilizing the cantilever and tip combination on a carrier, depositing a refractory metal on the silicon tip, heating the cantilever and tip combination in an ambient free of oxygen to react chemically the refractory metal on and the silicon of the tip, selectively etching any unreacted refractory metal from the tip, and annealing the cantilever and tip combination in an ambient free of oxygen. The method may also include, as a final step, removing any unreacted refractory metal from the tip.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: October 31, 2000
    Assignee: International Business Machines Corporation
    Inventors: Lambert A. Doezema, Philip V. Kaszuba, Leon Moszkowicz, James M. Never, James A. Slinkman