Patents by Inventor Philip W. Hon

Philip W. Hon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9431715
    Abstract: A flared feed horn including a plurality of signal lines deposited on a bottom surface of a substrate and forming part of a TE11 sum mode launcher, a ground plane deposited a top surface of the substrate, and an outer conductor electrically coupled to the ground plane and having an internal chamber, where the conductor includes a flared portion and a cylindrical portion. The outer conductor includes an opening opposite to the substrate defining an aperture of the feed horn. The feed horn also includes an embedded conductor positioned within the chamber and being coaxial with the outer conductor, where the embedded conductor is in electrical contact with the plurality of signal lines. The feed horn also includes a TE12 difference mode launcher electrically coupled to the outer conductor proximate the aperture.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: August 30, 2016
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Arun K. Bhattacharyya, Gregory P. Krishmar-Junker, Philip W. Hon, Shih-en Shih, David I. Stones, Dah-Weih Duan, Loc Chau
  • Patent number: 9425110
    Abstract: A three-dimensional wafer level packaged (WLP) integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been bonded together to provide vertical circuit redundancy. The integrated circuits on each of the separate wafers are performance tested prior to the wafers being bonded together so as to designate good performing circuits as active circuit cells and poor performing circuits as inactive circuit cells. The inactive circuit cell for a particular pair of integrated circuits is metalized with a short circuiting metal layer to make it inoperable. The WLP integrated circuit implements a yield-enhancing circuit redundancy scheme on spatially uncorrelated wafers that avoids wasting valuable wafer x-y planar area, which provides cost savings as a result of more wafer area being available for distinct circuits on each wafer rather than sacrificed for traditional side-by-side redundant copies of circuits.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: August 23, 2016
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Jose G. Padilla, Philip W. Hon, Shih-En Shih, Roger S. Tsai, Xianglin Zeng
  • Patent number: 9425511
    Abstract: A coaxial feed horn including a dielectric substrate having at least one microstrip feed line deposited on a bottom surface of the substrate and a ground plane deposited on a top surface of the substrate. A cylindrical outer conductor is electrically coupled to the ground plane and an embedded conductor is coaxially positioned within the outer conductor, where the embedded conductor is in electrical contact with the microstrip line. A dielectric member is positioned within the outer conductor and includes a tapered portion extending out of the outer conductor at the aperture. In one embodiment, the dielectric member is a plurality of dielectric layers each having a different dielectric constant, where a first dielectric layer allows for propagation of a TE11 sum mode and a last dielectric layer is positioned proximate the antenna aperture and allows for propagation of a TE12 difference mode.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: August 23, 2016
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Gregory P. Krishmar-Junker, Philip W. Hon, Arun K. Bhattacharyya