Abstract: The present invention provides a synchronous buck switcher including a first loop, second loop, a current limit switch, a capacitor and an RS flip flop. The first loop includes an error amplifier (EA), a pulse width modulator (PWM), a PMOS device and an NMOS device. The second loop includes a second capacitor and a resistor connected between the output terminal of the EA and an input terminal of the EA. During a current limit event, a current limit pulse is applied to the current limit switch which allows the input voltage at the inverting terminal of the EA to follow the decreasing output voltage due to the current limit event. As a result, regulation occurs at this lower voltage at the inverting input of the EA. The inverting input of the EA is then charged back to the original reference voltage, resulting in a smooth recovery from current limit.

Abstract: An integrated circuit system comprising: forming a differential amplifier including: forming a first transistor, coupling a second transistor to the first transistor in a high gain configuration, and coupling a third transistor, having a low gain configuration, in parallel with the second transistor; and adjusting a gain of the differential amplifier by adjusting a ratio of the size of the second transistor to the size of the first transistor.

Abstract: An integrated circuit system comprising: forming an analog switch including: providing a current source for driving the analog switch, coupling a first source follower to the current source for forming a first input to the analog switch, coupling a second source follower to the current source for forming a second input to the analog switch, and coupling a switch to the first source follower and the second source follower for selecting the first input, the second input, or a combination thereof; and selecting a voltage output signal from the first source follower, the second source follower, or a combination thereof including isolating the first input from the second input.

Abstract: An integrated circuit system comprising: forming a differential amplifier including: forming a first transistor, coupling a second transistor to the first transistor in a high gain configuration, and coupling a third transistor, having a low gain configuration, in parallel with the second transistor; and adjusting a gain of the differential amplifier by adjusting a ratio of the size of the second transistor to the size of the first transistor.

Abstract: A pin-limited device includes a pattern-recognition circuit that detects a predetermined signal pattern transmitted on a supply pin of the device. The predetermined signal pattern is generated within the acceptable operating voltage range of the IC device (e.g., between the minimum and maximum acceptable system voltage levels utilized to control the internal circuitry of the device). Accordingly, the pin-limited IC device continues to operate within specifications while the predetermined signal pattern is transmitted on the selected power supply pin or pins. A test mode circuit generates a switch control signal in response to the predetermined signal pattern to connect an output pin of the device, for example, to an internal node of the device. The pattern recognition circuit sets a latch when the predetermined signal pattern is detected, and the latch is reset when the device is powered down then powered up.

Abstract: A circuit, method, and system for intelligently soft starting switching regulators are provided. The circuit, method, and system provide for a switching circuit operable to couple an input voltage to an output of the switching regulator in response to a control signal, a controller operable to generate the control signal to control the switching of the switching circuit based in part on a reference voltage, and a soft start circuit operable to provide the reference voltage to the controller responsive to the switching of the switching circuit.

Abstract: A voltage monitor circuit for monitoring a first voltage includes a switch and a comparator. The switch has a first position and a second position. When the switch is in the first position, the switch connects the comparator to a first voltage terminal to monitor a second voltage. When the switch is in the second position, the switch connects the comparator to a second voltage terminal to monitor a third voltage. The second and third voltages are scaled voltages of the first voltage to be monitored. The comparator provides an output signal indicating a status of the first voltage, that is, whether the first voltage is within an operative range. The voltage monitor circuit may further include a voltage divider connected between the first voltage and a ground potential. The voltage monitor circuit of the present invention can be incorporated in an electrical system for monitoring a battery voltage.

Abstract: A voltage reference circuit includes a first transistor and a second transistor having their control terminals connected together, a first resistor coupled to a first current handling terminal of the first transistor, a second resistor coupled between an output node and a second current handling terminal of the second transistor, and a current mirror. The reference circuit provides an output voltage that is independent of variations in the supply voltage by adjusting the resistance of the first resistor in response to changes in the supply voltage. In one embodiment, the voltage at the control terminals of the first and second transistors is kept constant despite variations in the supply voltage. A first current and a second current flowing through the first and second transistors are also kept constant.

Abstract: A TTL input stage for negative supply voltage systems is described herein which obviates the need for a positive supply and a level shifter. In one embodiment, a first JFET current source, the emitter/collector of a PNP bipolar transistor, and a second JFET current source are connected in series between a control input and a negative supply voltage. The base of the bipolar transistor is connected to ground. At a control input of 2V.sub.be above ground, the PNP transistor has a V.sub.be drop across its emitter/base junction, and each of the identical JFETs has a V.sub.be drop across it. An NPN bipolar transistor, having its base connected to the source of the second JFET and its emitter connected to the negative voltage, is turned on by the V.sub.be drop across the second JFET to provide the output of the TTL input stage. In one embodiment, the TTL input stage is a control circuit for turning an output MOSFET on and off.

Abstract: A folder circuit maps an analog input voltage to an analog output voltage in accordance with a folding function having at least one folding point. The folder circuit includes a power supply node and at least one input differential stage. Each input differential stage has a first input node to which is applied the input voltage, a second input node to which is applied a first reference voltage corresponding to that stage's folding point, and two differential output nodes. A resistive network is connected between the power supply node and the two differential output nodes, and a current source draws a predefined current from each input differential stage. An output network generates an analog output voltage as a function of the highest voltages on the differential output nodes of all the stages of the folder circuit. A current injection circuit provides a level-shifting current to each input differential stage through the two differential output nodes.

Abstract: A voltage circuit, which provides a plurality of reference voltages, is formed from a resistive line having a first and second ends. The resistive line also includes a multiplicity of reference voltage tap points, and first and second sense points. The sense points are offset from the ends of the resistive line, and thus at least a plurality of the reference voltage tap points are located between the first sense point and the first end of the resistive line and another plurality of the reference voltage tap points are located between the second sense point and the second end of the resistive line. A plurality of other functional circuits, such as comparator circuits, are connected to various ones of the reference voltage tap points.

Abstract: An analog to digital converter includes first and second folder circuits that map an analog input voltage into first and second folder output voltages, using two different voltage transfer functions. First and second flash circuits generate first and second digital representations of the first and second folder output voltages. An MSB conversion circuit generates a set of most significant bits representative of the analog input voltage input, and a multiplexer selects one of the first and second digital representations in accordance with the least significant bit of the output from the MSB conversion circuit. The analog to digital converter further includes first and second decoder circuits for decoding the first and second digital representations from the two flash circuits, and the multiplexer selects one of the two decoded digital values. The selected decoded value represents the least significant bits of a digital representation of the analog input value.

Abstract: A high frequency sampling receiver circuit receives an analog input signal that is to be compared with a multiplicity of reference voltages. The receiver circuit includes a multiplicity of parallel sample and hold circuits, each having a respective sampling transistor connected between a respective sample holding node and a common input terminal. The receiver circuit is coupled to an array of comparator circuits, where each comparator has one input connected to one of the sample holding nodes and a second input connected to one of a sequence of reference voltages. A bias voltage circuit applies respective bias voltages to each of the sampling transistors such that the difference between the bias voltage of each sampling transistor and the reference voltage used by the corresponding comparator is approximately the same for all the sample and hold circuits.

Abstract: An N-bit analog to digital converter (ADC) generates an output code having J most significant bits (MSBs) and K least significant bits (LSBs). First and second folder circuits map an analog input voltage into first and second folder output voltages, each folder circuit having at least 2.sup.k +1 folding points. The folding points of the first folder circuit are located at 2.sup.k LSB+i.times.4.times.2.sup.k LSB for i=0 to 2.sup.k, while the folding points of the second folder circuit are located at 3.times.2.sup.k LSB+i.times.4.times.2.sup.k LSB for i=0 to 2.sup.k. Each folder circuit produces a folder output voltage as well as 2.sup.k +1 differential output voltages. An MSB decoder includes a comparator that compares the first and second folder output voltages to generate a second lowest MSB.

Abstract: An analog to digital converter (ADC) includes a primary folder circuit for mapping an analog input voltage to a folder output voltage, a voltage reference circuit for generating a plurality of reference voltages and a first array of comparators. Each of the comparators in the first comparator array includes a first input terminal to which is applied the ADC's analog input voltage and a second input terminal held at one of the reference voltages. The outputs of the comparators correspond to most significant bits of a digital representation of the analog input voltage. A plurality of reference folder circuits convert a plurality of the reference voltages into a corresponding plurality of comparison voltages. The ADC also includes a second array of comparators, each of which includes a first input terminal to which is applied the primary folder's output voltage and a second input terminal held at one of the plurality of comparison voltages.

Abstract: Circuitry is provided for effectively cancelling the offset voltage of a differential reset stabilized latch. The circuitry preadjusts the voltage on the latch's amplifier dual input nodes prior to application of the signal voltage to the latch input such that the positive amplifier input voltage is substantially equal to the positive output voltage and the negative amplifier input voltage is substantially equal to the negative output voltage.