Abstract: System in package (SiP) architectures using stitched reticle photonic integrated circuits (PICs), including a multi-die interconnect bridge (OMIB), are disclosed along with corresponding fabrication processes. A stitched multi-reticle OMIB provides an optically-enabled bridge between semiconductor dies referred to generally as XPUs where “X” is a variable representing a wide range of specialized processing units. The optically-enabled bridge enables high-speed, low-latency, and power-efficient communications using light to meet the bandwidth demands of modern artificial intelligence (AI) workloads. The disclosed SiP architectures use stacked arrangements in which the OMIBs are located directly under heat-producing elements of the XPUs.

Abstract: A device is disclosed that features a hybrid electro-photonic integrated circuit devices that include an electronic circuit layer mounted on a photonic circuit layer. In one aspect, a device includes a photonic circuit layer that includes photonic integrated circuits (PICs) that include a first PIC, a second PIC, and a third PIC. The second PIC is disposed between the first PIC and the third PIC. The first PIC includes one or more optical couplers. The photonic circuit layer includes waveguides arranged in the first PIC, the second PIC, and the third PIC. The device includes an electronic circuit layer including electronic integrated circuits (EICs) attached to the photonic circuit layer. The device includes electro-optical transceivers arranged in the electronic circuit layer and the photonic circuit layer. The waveguides include local waveguides and boundary-crossing waveguides that each extend across a boundary between adjacent PICs.

Abstract: A network switch is disclosed that features a hybrid electro-photonic integrated circuit devices that include an electronic circuit layer mounted on a photonic circuit layer. In one aspect, a switch includes a photonic circuit layer implemented in one or more first semiconductor chips. The photonic circuit layer includes a first inner region of the photonic circuit layer and a first outer region. The photonic circuit layer includes waveguides and one or more optical couplers in the first outer region. At least one waveguide is connected at one end to each of the one or more optical couplers. The switch also includes an electronic circuit layer implemented in one or more second semiconductor chips coupled to the one or more first semiconductor chips. The electronic circuit layer includes a second inner region adjacent to the first inner region of the photonic circuit layer and a second outer region.

Abstract: System in package (SiP) architectures using stitched reticle photonic integrated circuits (PICs), including a multi-die interconnect bridge (OMIB), are disclosed along with corresponding fabrication processes. A stitched multi-reticle OMIB provides an optically-enabled bridge between semiconductor dies referred to generally as XPUs where “X” is a variable representing a wide range of specialized processing units. The optically-enabled bridge enables high-speed, low-latency, and power-efficient communications using light to meet the bandwidth demands of modern artificial intelligence (AI) workloads. The disclosed SiP architectures use stacked arrangements in which the OMIBs are located directly under heat-producing elements of the XPUs.

Abstract: A device is disclosed that features a hybrid electro-photonic integrated circuit devices that include an electronic circuit layer mounted on a photonic circuit layer. In one aspect, an electronic circuit layer includes one or more semiconductor chips including computing components. The electronic circuit layer includes a first surface and a second surface opposite the first surface. The electronic circuit layer includes an inner region that includes an outer perimeter along the first and second surfaces. The inner region extends through the electronic circuit layer along a third dimension from the first surface to the second surface. The electronic circuit layer includes an outer region disposed between the outer perimeter of the inner region and an outer perimeter of the electronic circuit layer. The electronic circuit layer includes analog mixed signal blocks arranged in the inner region.

Abstract: A device is disclosed that features a hybrid electro-photonic integrated circuit devices that include an electronic circuit layer mounted on a photonic circuit layer. In one aspect, a device includes a photonic circuit layer that includes a first surface, a second surface opposite the first surface, waveguides, and photonic portions of electro-optical transceivers. The device includes an electronic circuit layer that includes a plurality of electronic integrated circuits (EICs) tiled together. Each EIC includes computing components, a first surface, a second surface opposite the first surface, electrical portions of electro-optical transceivers, and electrical channels. The device includes a crossbar switch that includes interconnects that electrically couple each EIC with each other adjacent EIC that is adjacent to the EIC. The interconnects include a set of bumps between the electronic circuit layer and the photonic circuit layer.

Abstract: A network switch is disclosed that features a hybrid electro-photonic integrated circuit devices that include an electronic circuit layer mounted on a photonic circuit layer. In one aspect, a switch includes a photonic circuit layer implemented in one or more first semiconductor chips. The photonic circuit layer includes a first inner region of the photonic circuit layer and a first outer region. The photonic circuit layer includes waveguides and one or more optical couplers in the first outer region. At least one waveguide is connected at one end to each of the one or more optical couplers. The switch also includes an electronic circuit layer implemented in one or more second semiconductor chips coupled to the one or more first semiconductor chips. The electronic circuit layer includes a second inner region adjacent to the first inner region of the photonic circuit layer and a second outer region.

Abstract: Multi-chip electro-photonic networks for interconnecting multiple circuit packages via photonic channels. Examples of a computing system include a first circuit package, a second circuit package, and one or more inter-chip bidirectional photonic channels interconnecting the first and second circuit packages. The first circuit package can include one or more memory nodes. The second circuit package can include multiple compute nodes and intra-chip bidirectional photonic channels interconnecting the compute nodes.

Abstract: A register may store a valid map indicator, a cache memory may store a plurality of cache entries, and a cache management circuit may perform a caching operation in response to receiving a memory access request that includes an address. The caching operation may include using a specific map to map the address to a cache entry in the cache memory in response to determining that the valid map indicator indicates the specific map. The cache management circuit my respond to the memory access request by returning data from the cache entry in response to determining that the cache entry includes a map indicator that equals the valid map indicator.

Abstract: Electro-photonic networks, including a plurality of processing elements connected by bidirectional photonic channels, suited for implementing neural-network models. Weights of the model may be preloaded into memory of the processing elements based on assignments of neural nodes to processing elements implementing them, and routers of the processing elements can be configured to stream activations between the processing elements based on a predetermined flow of activations in the model.

Abstract: One embodiment is a method that includes generating a request for a data item in a memory, obtaining the data item from the memory with a photonic interface, sending the data item to a fabric using a transmit unit of the photonic interface, and routing the data item through a portion of the fabric coupled to the memory, the portion of the fabric including one or more additional transmit and receive units between the photonic interface and a destination receive unit.

Abstract: Various embodiments provide for digital neural network (DNN) that form part of a machine learning (ML) processor and that perform a compute intensive function, such as convolutions or matrix multiplies, which can facilitate operation of a ML model. According to some embodiments, the DNN comprises a combinatorial tree that uses multiple-accumulate (MAC) units, and a sequencer that reads values from memory devices and feeds the combinatorial tree.

Abstract: Various embodiments provide for computational systems including multiple circuit packages, each circuit package comprising an electronic integrated circuit having multiple processing elements and intra-chip bidirectional photonic channels connecting the processing elements into an electro-photonic network, with inter-chip bidirectional photonic channels connecting the processing elements across the electro-photonic networks of the multiple circuit packages into a larger electro-photonic network.

Abstract: A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

Abstract: A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

Abstract: A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

Abstract: A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

Abstract: A device is disclosed that features a hybrid electro-photonic integrated circuit devices that include an electronic circuit layer mounted on a photonic circuit layer. In one aspect, a device includes a photonic circuit layer including a first surface, a second surface opposite the first surface, and photonic circuit portions tiled together to provide the photonic circuit layer. The photonic circuit layer includes electro-optical transceivers, one or more optical couplers, and waveguides. The waveguides include boundary-crossing waveguides that each extend across a boundary between adjacent photonic circuit portions. Each boundary-crossing waveguide includes an optical connection at the boundary. The optical connection has a width larger than a width of the waveguide away from the boundary. A first photonic circuit layer portion includes first and second electro-optical transceivers and first and second waveguides.

Abstract: Systems and methods for switching are disclosed. In an example, a switching system includes a photonic integrated circuit (PIC) having optical ports, an electric integrated circuit (EIC) stacked on the PIC and having switching circuitry, and photonic transceivers optically coupled to the optical ports of the PIC and electrically coupled to the switching circuitry of the EIC, and the switching circuitry is configured to transfer digital signals, which are generated from optical signals received at a first photonic transceiver of the photonic transceivers, to a second photonic transceiver of the photonic transceivers based on information in the digital signals, wherein the first photonic transceiver is optically coupled to a first optical port of the PIC and the second photonic transceiver is optically coupled to a second optical port of the PIC.

Abstract: Various embodiments provide for clock signal distribution within a processor, such as a machine learning (ML) processor, using a photonic fabric.