Patents by Inventor Philip Yashar
Philip Yashar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240112951Abstract: Integrated circuit interconnect structures including a niobium-based barrier material. In some embodiments, a layer of essentially niobium may be sputter deposited, for example to a thickness of less than 8 nm at a bottom of an interconnect via. A copper-based fill material may then be deposited over the niobium barrier material. Integrated circuit interconnect metallization may comprise some layers of metallization that have a tantalum-based barrier and other layers of metallization that have a niobium-based barrier.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Philip Yashar, Gokul Malyavanatham, Hema Vijwani
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Publication number: 20220157735Abstract: An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.Type: ApplicationFiled: January 27, 2022Publication date: May 19, 2022Inventors: Flavio GRIGGIO, Philip YASHAR, Anthony V. MULE, Gopinath TRICHY, Gokul MALYAVANATHAM
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Patent number: 11270943Abstract: An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.Type: GrantFiled: March 27, 2018Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: Flavio Griggio, Philip Yashar, Anthony V. Mule, Gopinath Trichy, Gokul Malyavanatham
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Publication number: 20220068802Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a first conductive interconnect line in a first inter-layer dielectric (ILD) layer above a substrate, a second conductive interconnect line in a second ILD layer above the first ILD layer, and a conductive via coupling the first conductive interconnect line and the second conductive interconnect line, the conductive via having a single, nitrogen-free tantalum (Ta) barrier layer. In another example, a method of fabricating an integrated circuit structure includes forming a partial trench in an inter-layer dielectric (ILD layer, the ILD layer on an etch stop layer, etching a hanging via that lands on the etch stop layer, and performing a breakthrough etch through the etch stop layer to form a trench and via opening in the ILD layer and the etch stop layer.Type: ApplicationFiled: December 23, 2020Publication date: March 3, 2022Inventors: Atul MADHAVAN, Gokul MALYAVANATHAM, Philip YASHAR, Mark KOEPER, Bharath BANGALORE RAJEEVA, Krishna T. MARLA, Umang DESAI, Harry B. RUSSELL
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Patent number: 10446439Abstract: An embodiment includes an apparatus comprising: a transistor formed on a substrate; and a metal interconnect formed in a dielectric layer above the transistor, wherein: the interconnect comprises a copper layer and a barrier layer that separates the copper layer from the dielectric layer, and the barrier layer comprises tantalum and niobium. Other embodiments are described herein.Type: GrantFiled: December 26, 2015Date of Patent: October 15, 2019Assignee: Intel CorporationInventors: Philip Yashar, Gokul Malyavanatham
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Publication number: 20190304918Abstract: An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.Type: ApplicationFiled: March 27, 2018Publication date: October 3, 2019Applicant: INTEL CORPORATIONInventors: Flavio Griggio, Philip Yashar, Anthony V. Mule, Gopinath Trichy, Gokul Malyavanatham
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Publication number: 20180327887Abstract: Refractory metal alloy targets for reducing particles in physical vapor deposition processing and refractory metal-based layer for integrated circuit applications (for example, crystallization barrier layers in non-volatile memory devices) are disclosed herein. An exemplary method for reducing particles in a PVD chamber include positioning a refractory metal alloy target in the PVD chamber, positioning a substrate in the PVD chamber a distance from the refractory metal alloy target, and sputtering material from the refractory metal alloy target to form a refractory metal-based layer over the substrate. The refractory metal alloy target includes a refractory metal (for example, tungsten or molybdenum) alloyed with a body-centered cubic (BCC) metal (for example, niobium, tantalum, vanadium, or a combination thereof). The BCC metal has a Young's modulus lower than a Young's modulus of the refractory metal.Type: ApplicationFiled: December 18, 2015Publication date: November 15, 2018Applicant: Intel CorporationInventors: Christopher J. WIEGAND, Philip YASHAR, Anurag CHAUDHRY
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Publication number: 20180301373Abstract: An embodiment includes a transmitter comprising: an oxide layer between a substrate and an epitaxial silicon layer; a modulator included within the silicon layer and a hybrid laser on the silicon layer; wherein (a) the silicon layer is thinner directly adjacent the modulator than directly adjacent the laser; and (b) the silicon layer comprises gratings directly under the laser and directly contacting the oxide layer. Other embodiments are described herein.Type: ApplicationFiled: December 26, 2015Publication date: October 18, 2018Applicant: Intel CorporationInventors: Philip Yashar, Gokul Malyavanatham
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Patent number: 8508018Abstract: Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB2. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.Type: GrantFiled: September 24, 2010Date of Patent: August 13, 2013Assignee: Intel CorporationInventors: Rohan N. Akolkar, Sridhar Balakrishnan, James S. Clarke, Christopher J. Jezewski, Philip Yashar
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Publication number: 20120077053Abstract: Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB2. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Inventors: Rohan N. Akolkar, Sridhar Balakrishnan, James S. Clarke, Christopher J. Jezewski, Philip Yashar
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Publication number: 20040063295Abstract: A method includes forming a first damascene interconnect layer in a first dielectric. A first dielectric film is deposited on the first dielectric and on the first damascene interconnect layer. A conductor layer is deposited on the first dielectric film. The conductor layer is patterned, via a single mask, to form a first conductor and a second conductor. The first damascene interconnect level, the first dielectric film, and the first conductor form a capacitor and the second conductor forms a resistor.Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Applicant: Intel CorporationInventors: Stephen T. Chambers, Rick Davis, Philip Yashar