Abstract: An arrangement for generating a transmission clock signal and a reception clock signal is proposed in which only a single voltage-controlled oscillator is used, the reception clock signal being generated by phase-adjusting means whereas the transmission clock signal is generated directly by the voltage-controlled oscillator. Cross-talk between a plurality of voltage-controlled oscillators can be prevented in this way. Also, various measures are proposed for optimizing a circuit of this kind.

Abstract: A device and method is described for the frequency division of an input clock signal, in which from the input clock signal at least two output clock signals are generated, with an output pulse frequency equal to an input pulse frequency divided by a given factor, whereby with a phase detector a phase difference is measured between the at least two output signals and each of the at least two output clock signals is either inverted or not inverted, as a function of the phase difference determined. A method of this type is particularly suitable for the demultiplexing of an input data signal, and can also be designed to be multi-step.

Abstract: A method and an apparatus for scanning a data signal are provided whereby a plurality of scanning signals (P0, P1, P2, P3) delayed successively by a respective phase difference are generated, for example, by a quadrature oscillator (1). A first data signal (D) is scanned with these scanning signals (P0–P3) in order to generate a plurality of second data signals (D0–D3). Because the direction of rotation of the quadrature oscillator (1) can vary, depending on random starting conditions, the direction of rotation is determined by means of phase detectors (4). These phase detectors (4) are preferably connected to the outputs of the clock dividers (3). Depending on the direction of rotation determined, the second data signals (D0–D3) are allocated to output channels (A0–A3) by a change-over unit (6).

Abstract: A device and method is described for the frequency division of an input clock signal, in which from the input clock signal at least two output clock signals are generated, with an output pulse frequency equal to an input pulse frequency divided by a given factor, whereby with a phase detector a phase difference is measured between the at least two output signals and each of the at least two output clock signals is either inverted or not inverted, as a function of the phase difference determined. A method of this type is particularly suitable for the demultiplexing of an input data signal, and can also be designed to be multi-step.

Abstract: An arrangement for generating a transmission clock signal and a reception clock signal is proposed in which only a single voltage-controlled oscillator is used, the reception clock signal being generated by phase-adjusting means whereas the transmission clock signal is generated directly by the voltage-controlled oscillator. Cross-talk between a plurality of voltage-controlled oscillators can be prevented in this way. Also, various measures are proposed for optimizing a circuit of this kind.

Abstract: A method and an apparatus for scanning a data signal are provided whereby a plurality of scanning signals (P0, P1, P2, P3) delayed successively by a respective phase difference are generated, for example, by a quadrature oscillator (1). A first data signal (D) is scanned with these scanning signals (P0-P3) in order to generate a plurality of second data signals (D0-D3). Because the direction of rotation of the quadrature oscillator (1) can vary, depending on random starting conditions, the direction of rotation is determined by means of phase detectors (4). These phase detectors (4) are preferably connected to the outputs of the clock dividers (3). Depending on the direction of rotation determined, the second data signals (D0-D3) are allocated to output channels (A0-A3) by a change-over unit (6).