Abstract: A method is provided for fabricating an avalanche photodiode (APD) device, in particular, a separate absorption charge multiplication (SACM) APD device. The method includes forming a first contact region and a second contact region in a semiconductor layer. Further, the method includes forming a first mask layer above at least a first contact region of the semiconductor layer adjacent to the first contact region, and forming a second mask layer above and laterally overlapping the first mask layer. Thereby, a mask window is defined by the first mask layer and the second mask layer, and the first mask layer and/or the second mask layer are formed above a second contact region of the semiconductor layer adjacent to the second contact region.

Abstract: A method is provided for fabricating an avalanche photodiode (APD) device, in particular, a separate absorption charge multiplication (SACM) APD device. The method includes forming a first contact region and a second contact region in a semiconductor layer. Further, the method includes forming a first mask layer above at least a first contact region of the semiconductor layer adjacent to the first contact region, and forming a second mask layer above and laterally overlapping the first mask layer. Thereby, a mask window is defined by the first mask layer and the second mask layer, and the first mask layer and/or the second mask layer are formed above a second contact region of the semiconductor layer adjacent to the second contact region.

Abstract: A method for fabricating an integrated semiconductor photonics device is disclosed. The method may include providing a first substrate having on its top surface a monocrystalline semiconductor layer suitable for supporting an optical mode and forming a homogenous and conformal first dielectric layer on a planar surface of the monocrystalline semiconductor layer. The method may further include providing a dielectric waveguide core on the first dielectric layer, the dielectric waveguide core optically coupled to a first region of the monocrystalline semiconductor layer through the first dielectric layer. The method may further include depositing a second dielectric layer on the dielectric waveguide core, thereby covering the dielectric waveguide core, and annealing the substrate to drive hydrogen out of the dielectric waveguide core.

Abstract: Semiconductor photonics devices for coupling radiation to a semiconductor waveguide are described. An example photonics device comprises a semiconductor-on-insulator substrate comprising a semiconductor substrate, a buried oxide layer positioned on top of the semiconductor substrate, and the semiconductor waveguide on top of the buried oxide layer to which radiation is to be coupled. The example device also comprises a grating coupler positioned on top of the buried oxide layer and configured for coupling incident radiation to the semiconductor waveguide. The semiconductor substrate has a recessed portion at the backside of the semiconductor substrate for receiving incident radiation to be coupled to the semiconductor waveguide via the backside of the semiconductor substrate and the grating coupler.

Abstract: A method for fabricating an integrated semiconductor photonics device is disclosed. The method may include providing a first substrate having on its top surface a monocrystalline semiconductor layer suitable for supporting an optical mode and forming a homogenous and conformal first dielectric layer on a planar surface of the monocrystalline semiconductor layer. The method may further include providing a dielectric waveguide core on the first dielectric layer, the dielectric waveguide core optically coupled to a first region of the monocrystalline semiconductor layer through the first dielectric layer. The method may further include depositing a second dielectric layer on the dielectric waveguide core, thereby covering the dielectric waveguide core, and annealing the substrate to drive hydrogen out of the dielectric waveguide core.

Abstract: Semiconductor photonics devices for coupling radiation to a semiconductor waveguide are described. An example photonics device comprises a semiconductor-on-insulator substrate comprising a semiconductor substrate, a buried oxide layer positioned on top of the semiconductor substrate, and the semiconductor waveguide on top of the buried oxide layer to which radiation is to be coupled. The example device also comprises a grating coupler positioned on top of the buried oxide layer and configured for coupling incident radiation to the semiconductor waveguide. The semiconductor substrate has a recessed portion at the backside of the semiconductor substrate for receiving incident radiation to be coupled to the semiconductor waveguide via the backside of the semiconductor substrate and the grating coupler.

Abstract: A method is described for improving the uniformity over a predetermined substrate area of a spectral response of photonic devices fabricated in a thin device layer. The method includes (i) establishing an initial device layer thickness map for the predetermined area, (ii) establishing a linewidth map for the predetermined area, and (iii) establishing an etch depth map for the predetermined area. The method further includes, based on the initial device layer thickness map, the linewidth map and the etch depth map, calculating an optimal device layer thickness map and a corresponding thickness correction map for the predetermined substrate area taking into account photonic device design data. Still further, the method includes performing a location specific corrective etch process in accordance with the thickness correction map.

Abstract: Disclosed are methods for co-integration of active and passive photonic devices on a planarized silicon-based photonics substrate. In one aspect, a method is disclosed that includes providing a planarized silicon-based photonics substrate comprising a silicon waveguide structure, depositing a dielectric layer over the planarized silicon-based photonics substrate, selectively etching the dielectric layer, thereby exposing at least a portion of the silicon waveguide structure, selectively etching the exposed portion of the silicon waveguide structure to form a template, using the silicon waveguide structure as a seed layer to selectively grow in the template a germanium layer that extends above the dielectric layer, and planarizing the germanium layer to form a planarized germanium layer, wherein the planarized germanium layer does not extend above the dielectric layer.

Abstract: A method is described for improving the uniformity over a predetermined substrate area of a spectral response of photonic devices fabricated in a thin device layer. The method includes (i) establishing an initial device layer thickness map for the predetermined area, (ii) establishing a linewidth map for the predetermined area, and (iii) establishing an etch depth map for the predetermined area. The method further includes, based on the initial device layer thickness map, the linewidth map and the etch depth map, calculating an optimal device layer thickness map and a corresponding thickness correction map for the predetermined substrate area taking into account photonic device design data. Still further, the method includes performing a location specific corrective etch process in accordance with the thickness correction map.

Abstract: Disclosed are methods for co-integration of active and passive photonic devices on a planarized silicon-based photonics substrate. In one aspect, a method is disclosed that includes providing a planarized silicon-based photonics substrate comprising a silicon waveguide structure, depositing a dielectric layer over the planarized silicon-based photonics substrate, selectively etching the dielectric layer, thereby exposing at least a portion of the silicon waveguide structure, selectively etching the exposed portion of the silicon waveguide structure to form a template, using the silicon waveguide structure as a seed layer to selectively grow in the template a germanium layer that extends above the dielectric layer, and planarizing the germanium layer to form a planarized germanium layer, wherein the planarized germanium layer does not extend above the dielectric layer.

Abstract: A method for manufacturing a dual workfunction semiconductor device and the device made thereof are disclosed. In one aspect, the method includes manufacturing a first transistor in a first region and a second transistor in a second region of a substrate, the first transistor including a first gate stack, the first gate stack having a first gate dielectric capping layer and a first metal gate electrode layer. The second gate stack is similar to the first gate stack. The method includes applying a first thermal budget to the first gate dielectric capping layer and a second thermal budget to the second gate dielectric capping material to tune the workfunction of the first and second gate stack, the first thermal budget being smaller than the second thermal budget such that after the thermal treatment the first and the second gate stack have different work functions.

Abstract: A method for manufacturing a dual workfunction semiconductor device and the device made thereof are disclosed. In one aspect, the method includes manufacturing a first transistor in a first region and a second transistor in a second region of a substrate, the first transistor including a first gate stack, the first gate stack having a first gate dielectric capping layer and a first metal gate electrode layer. The second gate stack is similar to the first gate stack. The method includes applying a first thermal budget to the first gate dielectric capping layer and a second thermal budget to the second gate dielectric capping material to tune the workfunction of the first and second gate stack, the first thermal budget being smaller than the second thermal budget such that after the thermal treatment the first and the second gate stack have different work functions.

Abstract: A plurality of mask images defines an optical circuit image in photoresist. Each of the mask images comprises parts of the optical circuit and the totality of all mask images together defines an optical circuit. The optical circuit is thus made up of plural optical elements some of which may be positioned in drop-in locations within the boundary of another optical circuit element. A photolithography system globally aligns and exposes the mask images in photoresist. The resultant composite image is substantially indistinguishable from a single image of the entire optical circuit. Different images for each of the mask image parts can be substituted with other images or image parts and thereby exponentially increasing the number of circuit permutations from a predetermined number of available mask images. A unique optical circuit, for example, can be generated from a pre-existing library of reticle images. The images are printed in predetermined locations on a substrate to define the desired optical circuit.

Abstract: A method is described for forming an at least partially silicided contact. In one embodiment, a hardmask is deposited over a contact. A coating of sacrificial material is then provided on top of the hardmask. The sacrificial material coating is etched back until the top of the contact is exposed. The contact is then opened, the sacrificial material is removed, and a silicidation of the contact is performed.

Abstract: A method for forming an optical circuit on a substrate. The method comprising a plurality of mask images to define the optical circuit image in photoresist. Each of the mask images defining parts of the optical circuit and the totality of all mask images substantially defining all of the optical circuit. A photolithography system globally aligns and exposes the mask images in photoresist. The resultant composite image being substantially indistinguishable from a single image of the entire optical circuit. Different images for each of the parts can be substituted by other images, thereby exponentially increasing the number of circuit permutations from a predetermined number of images. The method is also applicable to generating a unique circuit from a pre-existing library of reticle images. The images are printed in predetermined locations on a substrate to define the desired optical circuit.

Abstract: A manufacturing process is provided for fabrication of vertically coupled integrated photonic devices by projection lithographic technique. A multi-layered structure is formed which includes a pair of core waveguiding layers separated by a coupling interlayer and sandwiched between cladding layers. Prior to forming optical features in the core layers, alignment marks are etched completely through the whole multi-layered structure with the alignment marks being visible on both sides of the multi-layered structure to a conventional projection stepper. After the alignment marks are formed, a “bottom level” optical features are made through the bottom cladding layer, bottom core layer, and portion of intervening coupling layer. The formed sample is then bonded by a polymer to a carrier and a “top level” optical features are defined through the top cladding, top core layer, and portion of the intervening coupling layer.

Abstract: A manufacturing process is provided for fabrication of vertically coupled integrated photonic devices by projection lithographic technique. A multi-layered structure is formed which includes a pair of core waveguiding layers separated by a coupling interlayer and sandwiched between cladding layers. Prior to forming optical features in the core layers, alignment marks are etched completely through the whole multi-layered structure with the alignment marks being visible on both sides of the multi-layered structure to a conventional projection stepper. After the alignment marks are formed, a “bottom level” optical features are made through the bottom cladding layer, bottom core layer, and portion of intervening coupling layer. The formed sample is then bonded by a polymer to a carrier and a “top level” optical features are defined through the top cladding, top core layer, and portion of the intervening coupling layer.